So I'm trying to wire up a full adder just with NPN BJT transistors (I know there is a 74XX283 4-bit binary full adder, but I want to do it just with transistors if possible for my own learning).

The full adder I'm trying to build looks like the following with logic gate symbols:

enter image description here

Image from Wikipedia

I use a NAND, OR and AND gate to build the XOR gate:

enter image description here

Image from Wikipedia

Right now my current circuit looks like this:


simulate this circuit – Schematic created using CircuitLab

Schematic notes:

But the circuit does not work as intended:

A B CIn | Sum COut
0 0 0   | 0   0   (Both LEDs are clearly off)
0 0 1   | 1   0   (A clear one the LED glows; the other is off)
0 1 0   | 1/2 0   (The LED just glows like half; the other is off)
1 0 0   | 1/2 0   (The LED just glows like half; the other is off)
1 1 0   | 0   1/2 (The LED just glows like half; the other is off)
1 0 1   | 0   1/8 (The LED just barely glows; the other is off)
0 1 1   | 0   1/8 (The LED just barely glows; the other is off)
1 1 1   | 1   1   (Both LEDs only glow half)

The expected behaviour would be:

A B CIn | Sum COut
0 0 0   | 0   0
0 0 1   | 1   0
0 1 0   | 1   0
1 0 0   | 1   0
1 1 0   | 0   1
1 0 1   | 0   1
0 1 1   | 0   1
1 1 1   | 1   1

I have tried to remove, change or add some pull down resistors on the gate outputs, but the above circuit is the best attempt I have right now. I have also changed out all components and the breadboard I use, just to make sure it isn't some component that is dead. I already have double/triple checked all resistors and connections, so that I don't just have a misplaced wire or wrong resistor.

I also tried to use a multimeter to find the error, but that just confused me more. But if I have to I can also check stuff with the multimeter if necessary.

So I'm at the end with my knowledge here how to fix my circuit design and get a clear on and off output?

I don't know if I use wrong resistor values, I don't use the transistors correctly or if my design is wrong from the start.

  • \$\begingroup\$ Try simulating it in LTSpice or some other free sim tool. The problem is that the circuit just isn't that interesting to most seasoned EEs so the only folk who might help are those interested in building something this historical hence why I suggest a sim tool. Start with logic gates and get that working then replace each gate with BJTs and advance, debug, fix, advance, debug, fix etc... \$\endgroup\$ – Andy aka Oct 25 '16 at 17:07
  • 1
    \$\begingroup\$ You have your whole circuit in Circuit Lab already, have you used their simulator to see if it works as expected? \$\endgroup\$ – Tyler Oct 25 '16 at 17:16
  • \$\begingroup\$ @Tyler Not yet, but I can give it a try if I get it running. \$\endgroup\$ – Rizier123 Oct 25 '16 at 17:21
  • \$\begingroup\$ I ran it with your first 1/2 lit scenario, and got -415mV on the Sum LED, work backwards from there, maybe. \$\endgroup\$ – Tyler Oct 25 '16 at 17:26
  • 2
    \$\begingroup\$ The problem with this circuit is that the BJT 'gate' circuits are poorly designed and do not interface correctly. eg. the basic NAND gate is made from two BJTs - the bottom one works as a switch, the top one works as an emitter follower.Inputs require a source of current but outputs sink current. Problems are simply compounded when the 'gates' are connected together and you end up getting all sorts of funny voltages produced rather than a logic signal. You'll waste lots of time and effort and it just won't work. Andy gives excellent advice. \$\endgroup\$ – JIm Dearden Oct 25 '16 at 19:03

It's probably most straight forward using a NOR form as the basis of a BJT adder. It's quite simple to form the basic gate, this way. Nothing crazy, at all. Just simplicity.

The following schematic shows the basic one-BJT form for the NOR gate at the top. It then follows up by showing what a full adder would look like if it were based entirely on these gates. You'd need a total of 9 NPN BJTs here. Half of what you are using now. And it should actually work okay and simulate fine. (You may get glitching. But if you observe reasonable setup and hold times, it should work okay.)


simulate this circuit – Schematic created using CircuitLab

Also, the inputs as designed don't overload the outputs. There are, at most, three input loads on a single output (in two cases.) The rest is either one or two loads.

Here's an LTspice circuit and simulation, walking through all eight combinations of A, B, and C.

adder simulation

  • \$\begingroup\$ But where did I went wrong with my design? What mistakes did I do? I would like to learn from the mistakes I made in my current design. If possible I don't want to build the adder just out of universal NOR gates. \$\endgroup\$ – Rizier123 Oct 25 '16 at 19:12
  • \$\begingroup\$ @Rizier123 Why not? You wrote, "the circuit does not work as intended." I repaired that problem. So what is your real goal here, if not to design a working full adder out of BJTs? I don't understand your real goals, I suppose. But you obviously haven't stated them, now that you are asking this question. \$\endgroup\$ – jonk Oct 25 '16 at 19:15
  • \$\begingroup\$ Well it just fells a bit weird to use only one kind of gate. And if I use the same gates as in my schematic just with ICs it works, but if I try to build the gates my own with transistors it doesn't. \$\endgroup\$ – Rizier123 Oct 25 '16 at 19:20
  • 1
    \$\begingroup\$ @jonk you know you are in good company in that adder design? NASA did that (well much more actually). The Apollo guidance computer was totally based on an RTL dual NOR gate here picture, schematics and usage example \$\endgroup\$ – carloc Oct 25 '16 at 19:28
  • 1
    \$\begingroup\$ @Rizier123 I didn't want to go sitting around investigating the use of 18 BJTs in an adder, when it was so much easier to just make a working example using far fewer BJTs. So your question is really "what's wrong with my thinking process" and not "building a full adder with NPN BJT transistors," as I'd earlier imagined? I'll give it a shot as an addendum. \$\endgroup\$ – jonk Oct 25 '16 at 20:07

As you can make the other gates from NAND gates try this (circuit is based upon a simplified TTL (DTL) type gate. Note that the inputs a current source, outputs sink current.

The transistors are jelly bean types e.g. BC548 (NPN), BC557 (PNP)

enter image description here


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.