# Understanding DAC specs

I am confused on how the specs of a DAC work together.

I am looking at this one: http://www.ti.com/lit/ds/symlink/dac7811.pdf for a project and am wondering how the sampling rate (5 MSPS), the serial clock rate (50 MHz) and the resolution (12bits) all work together.

Where I'm getting lost is how the resolution and the sampling frequency work together. If my fs is 5 MHz, does this mean that I have 12 bits to represent 5M worth of values? Or does each single sample in the 5 M samples have a possible value from -=2^12?

This particular DAC has a 16 bit register with the first 4 being control registers, so what exactly goes into the last 12? They're binary values, so how can that accurately represent a signal being sampled at 5 MSPS? I know that the clock can operate at a max of 50MHz, which is how fast the DAC can send packages back and forth from my micro-controller. Does this value have anything to do with sampling rate or resolution?

I've been all over google and wikipedia for this and have checked with other students who aren't quite sure either. Can anyone offer clarification?

Edit to add: here is the link to the Newark.com page for this part where it specified 5 MSPS http://www.newark.com/texas-instruments/dac7811idgsr/digital-to-analog-converter-dac/dp/85K0568

• Where in the specs did you see the "5MSPS" sampling rate? Commented Oct 25, 2016 at 21:40
• I found this product via the Newark.com website where 5 MSPS was the sampling rate specified for it. Commented Oct 25, 2016 at 21:41

Each sample is 12 bits, giving one of 4096 possible values. There are 4 additional bits attached to each sample for control purposes.

With an input clock rate of 50 MHz, that means the maximum sample rate isn't 5 MHz, (I don't know where you got that from) but 50MHz/16 = 3.125MHz.

And your MCU needs to feed it at that rate : 16 bits, 3.125 million times per second, if you want to achieve that sample rate. It's perfectly OK to run it at a lower rate, of course. There are 2 ways to do that : either use a slower clock on the SPI interface, or by only asserting SYNC less often.

• 5 MSPS came from the Newark.com site that I found this product through. I searched for a specific sample rate and this is one of the products that came up. Commented Oct 25, 2016 at 21:45
• Newark may have classed it as "in the region of" 5 MHz. If that is your actual speed requirement, this DAC will not do (unless you interleave 2 of them)
– user16324
Commented Oct 25, 2016 at 21:50
• Oh. Well, that's news to me. I need something from 4-5 MSPS. Is there a better way to search? Edit: Wait, wouldn't it be 50MHz/12? Why include the 4 control bits in determining sampling frequency? Commented Oct 25, 2016 at 21:53
• Because to cause the DAC to update, you have to send it 16 bits. Only 12 of those bits are converted to the value placed on the output, but it needs all 16 to determine how to do that. Commented Oct 25, 2016 at 22:01

DAC stands for Digital-to-Analog Converter. As the name implies, your system pushes a digital value into the converter, and the converter produces analog signal with DC amplitude proportional to the digital code. The DAC takes 12 bit of data, no more.

How it works together?

1. This particular DAC takes digital data in serialized format, it is a low pin count IC. The serial interface runs at 50MHz clock.
2. Your MCU must have the corresponding converter to supply the serial stream of data, in format described in DAC's specification;
3. The format of data is FIXED at 16bit, where the low 12 are actual data, and 4 are some service data. Each time the MCU must send new 16-bit serial packet, the DAC will output new DC analog value. The DAC does not send any data back.
4. How fast the DAC can operate (change output)? The transmission of the 16-bit control world of data takes about 20 interface clocks, according to the spec diagram. It means that it takes 20 * 20ns = 400 ns to output new value at DAC's output. This means that the output signal cannot be updated faster than 2.5 MS/s.
• I put an estimated 20 clock times because the protocol requires extra SYNC bit to be transmitted at the beginning of data word, and some turn-around clock may be required. It is not clear how fast a back-to-back transmission can occur, but it definitely less than 5MSPS Commented Oct 25, 2016 at 22:14
• How did you get 20 clock cycles? To me it looks like 16 clock cycles and 200ns results in 3.125MSPS as Brain Drummond said below. Commented Oct 25, 2016 at 22:17
• Could you please check your arithmetic? 50MHz = 20ns clock cycle. Commented Oct 25, 2016 at 22:37
• Erps, I used 5. My bad. Yes that would make more sense. Commented Oct 25, 2016 at 22:42