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I have used digital Isolators before in unidirectional Designs. I am now faced with isolating a bidirectional digital signal line. Specifically I would like to isolate the 2-wire debug interface of an STM32 and the STlinkV2. I have found a circuit that claims to be able to do this for a generic ARM Cortex. It uses an SI8662 6-ch, digital Isolation IC.

Here is my schematic: My schematic

I have implemented the design on a prototype pcb. The unidirectional CLK signal arrives in quite a good condition after the isolator. The bidirectional Data signal however is severely degraded. Obviously this is due to the chain of the two isolator channels that feed back into the signal with a delay.

Here is a scope image of the Data line after the isolation IC: Here is a scope image of the Data line after the isolation IC

My understanding of the cicuit is, that the 4k7 Resisors dampen the feedback signal and therefor the feedback should not be visible if the line is not driven at the outher side of the isolator. Is this correct? If so, how would one choose the values for these resistors?

If this is bad way to do it, is there any other approach to isolate bidirectional data lines?

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    \$\begingroup\$ Seems like a funny place to need or want isolation. I'd encourage you to take a step back, draw some architecture diagrams, and figure out if there's a more appropriate level to isolate at. \$\endgroup\$ – Scott Seidman Oct 25 '16 at 23:35
  • \$\begingroup\$ Bi-directional isolation is tricky -- one way is having something intelligent enough to run a state machine and flip output enables as needed. There are USB isolators available that might be suitable for this purpose -- I don't know off hand how they've been implemented, though. Could be worth a quick check. \$\endgroup\$ – Krunal Desai Oct 25 '16 at 23:42
  • \$\begingroup\$ The lower limit of the resistance is probably dictated by the current drive level of the SWDIO pins. For example, if you don't want those pins to drive more than 3.3mA, then the resistor should be 1K or higher. \$\endgroup\$ – rioraxe Oct 26 '16 at 4:28
  • \$\begingroup\$ The other limit is when the isolation IC is driving, the resistance along with the capacitance of the lines would determined the edge rates. If the recombined nodes SW_DIO_1 or SW_DIO_2 are driving a cable, the capacitance can be high and that can lead to no room to set the resistance. A possible way to reduce the capacitance of the recombined node is to move that (the resistors) as close to the corresponding SWDIO pin as possible. \$\endgroup\$ – rioraxe Oct 26 '16 at 4:48
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    \$\begingroup\$ Why do you not use a Si8606AC-B-IS1? It should work for the SWD IO signal \$\endgroup\$ – rfkortekaas Oct 26 '16 at 16:42
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Using galvanic isolation with a bidirectional signal is difficult. It would be much easier with a data flow direction signal that enables XMTR and RCVR of only one direction and disables the other direction. If the data flow direction is changed, there should be a short gap with both directions disabled.

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Ok thank you all for your input. I tried a bunch of different Resistors but in the end was not able to get the signal isolated this was.

Thank you very much rfkortekaas for suggesting the Si8606AC-B-IS1, i overlooked this chip. I ordered some and tried to isolate SWDIO with it an it worked very nicely!

This provides me with a very cheap alternative to an USB-Isolator and I can use my laptop in a test environment without worrying to much about any damage to it while debugging.

Thanks all for your help!

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