Are there any free or open source synthesis tools available that can convert Verilog RTL into a generic gate netlist? (composed of generic NAND, NOR, XOR, D-flops/registers, etc. Optimization not required.). If not for the full language, how about for a "useful" subset of RTL (beyond merely a Verilog gate level netlist)?
Icarus Verilog, OSS tool, very handy, even has a simulator. http://iverilog.icarus.com/
Its a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. For synthesis, the compiler generates netlists in the desired format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-2005.
Icarus Verilog is a work in progress, and since the language standard is not standing still either, it probably always will be. That is as it should be. However, I will make stable releases from time to time, and will endeavor to not retract any features that appear in these stable releases.
The main porting target is Linux, although it works well on many similar operating systems. Various people have contributed precompiled binaries of stable releases for a variety of targets. These releases are ported by volunteers, so what binaries are available depends on who takes the time to do the packaging. Icarus Verilog has been ported to That Other Operating System, as a command line tool, and there are installers for users without compilers. You can compile it entirely with free tools, too, although there are precompiled binaries of stable releases.
I think your need is best served by HDL Analyzer and Netlist Architect (HANA) : https://sourceforge.net/projects/sim-sim/files/ It supports almost whole of Verilog 1995-2001 constructs. It generates output in terms of generic gates in Verilog format. Also you can specify technology library to be mapped to. It has its own library format.