I recently took an oscilloscope to a reset circuit on a new board I am working on (derivative of WildFire). Nothing earth shattering here, U6 is an Atmel ATMega1284P (VCC=5V), and U8 is an FTDI FT231X (VCCIO=3.3V, 5V-tolerant). The relevant parts of the schematic are:
and here is a scope trace of what happens when DTR goes low on the FTDI chip.
The blue line is DTR, the yellow line is RESET (never mind the labels). When DTR goes low, it looks to me from the scope, that the RESET signal doesn't get all the way to GND, reaching a minimum at the cusp of about 1.72V before 'discharging' back to 5V.
The thing is, the ATMega1284P is certainly resetting as intended, but I'm concerned that it's not reaching a low enough voltage to be in spec for a reset. The datasheet says that Vlow for RESET is 0.1*Vcc, which would be 0.5V @ Vcc=5V, and I'm a good 1V above that apparently.
So, (1) can you explain why RESET doesn't get all the way to GND, and (2) can you suggest a fix, without changing the design fundamentally, that will get RESET to drop below 0.5V when DTR transitions from 3.3V to GND? I'm imagining the shape of this fix to be something like change R11 to a different value, or change C24 to a different value. Or some combination theretofore.
Or am I just seeing a measurement artifact? You can't really see it behind the cursor bubble on the scope trace, but when DTR transitions from GND to 3.3V, it looks like RESET exhibits an inverse signal, rising to about 6.48V and then 'discharging' to 5V. I'm not seeing how that is a predicted outcome of the circuits in play here.
EDIT Writing a question down thoughtfully makes it stare you in the face sometimes. It's because DTR is at 3.3V and RESET is at 5V. So the most that C24 can pull down reset is by 3.3V, which leaves a residue of 1.7V.
So the updated question is how would you fix this? Pull the ATmega1284P reset up to 3.3V instead of 5V?