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Schmitt Trigger CMOS

How does this circuit work? Why do you get different threshold voltages for increasing and decreasing Vin?

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  • \$\begingroup\$ What do you know about these FETs? \$\endgroup\$ Oct 27, 2016 at 3:03
  • \$\begingroup\$ Only that P:N ratio is 2:1 \$\endgroup\$
    – VaidVaid
    Oct 27, 2016 at 3:14

3 Answers 3

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This circuit is typically used to change the trip point of a standard inverter. If you look closely you'll find that the size of the feedback MOSFETs play a major role in deciding the Vin at which the output will switch from low to high or vice-versa.

Vih, is the input voltage at which the output switches from high to low. The source voltage of N2 is reponsible for that. Now the N2 source voltage depends on the output voltage, size of the feedback nmos. The more the width of feedback nmos N3, lower will be the Vih. Same holds true for the low to high condition in the Pmos side (which affects the Vil).

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  • These FETS would use Vgs of 1.5V so that P3 and N3 switch their respective sources to between 3.5~5V and 0~3.5
  • the N12P12 gates are wired as "AND" logic with N3P3 forming 2 inversions and positive feedback to shift the levels for Vgs on N2P2
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  • \$\begingroup\$ If Vdd exceeds twice the gate-source threshold voltage, it would seem that if the output is high and the input is at Vdd/2, there would be a Vdd->Vss path through N3 and N1. Perhaps one could size components so as to limit the current, but that seems rather dodgy to me. \$\endgroup\$
    – supercat
    Aug 22, 2017 at 21:14
  • \$\begingroup\$ I believe all logic is designed this way with controlled RdsOn during crossover to limit transition current. \$\endgroup\$ Aug 22, 2017 at 21:45
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Suppose, Vin=0 and Vo was 1. That means N3 has pulled its source terminal to logic high. Now as Vin increases gradually, and reaches the Vt of NMOSes (assuming all Nmos have same Vt), N1 turns on in saturation but N2 turns on in linear region (deep triode). Which means it conducts almost no current. So you have to even further increase Vin so that N1 able to conduct enough current to have both N1 and N2 goes to saturation. By then, as N3 is a week transistor, would be hardly conducting as output node voltage decreases. So basically, High to Low trip point is increased as compared to what it is in normal CMOS inverter.

Similarly when Vin goes down from 1 to 0, P1 turns on in saturation region, but P2 turns on in deep triode region (because weak P3 was initially ON). And you need to reduce Vin even more than conventional to completely pull up the circuit.

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