I have a non-inverting op-amp circuit with each branch having a resistor and capacitor in parallel. The op-amp I am using is a LM741. The circuit works as expected for sinusoidal inputs up to 10 kHz, but once it reaches 20 kHz, the gain suddenly increases more than expected. Can someone please explain why this is happening? (i.e. why is there the little hump in the bode plot?).
As I have mentioned in my short comment already - the reason for the peak is the phase margin that is too low (according to my simulation only app. 10-15 deg.). Therefore, we have gain peaking of app. 20 dB at app. 250kHz.
This peaking is mainly caused by the input capacitor of 47nF (in conjunction with the opamps frequency characteristics). This capacitor causes an additinal phase lag (feedback factor reduction) in the critical frequency range (where the loop gain is very small). For example, a reduction to 4.7nF gives an increased phase margin of app 40 deg. and a gain peaking of app. 5 dB only.
Of course, this effect must be seen in connection with the open-loop response of the opamp (in particular, with the high-frequency poles, as mentioned by owg60). Another opamp with a larger transit frequency will certainly show a better performance.
Note: All simulations were performed using the LM741NS SPICE model.
EDIT (question): Why 15 dB gain (theoretical) for large frequencies?
The 741 is compensated such that it has a dominant pole around 10Hz. If you figure its low frequency gain is about 100db, at 100kHz it only has 20db left. It is not looking like much of an opamp at this point. It has additional higher frequency poles. I did a quick poll zero analysis of your circuit and found a complex pair at W=39K+/-j730k. this is a little different than your peak but that could be model differences. If your simulator will do a poll/zero analysis it will show a complex pair around the peak you are seeing.