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I'm learning about synthesis of VHDL code and I have the doubt about the advantages and disadvantages of Hierarchichal vs Flatten netlists. The first is like interconnection of blocks and the second one is like all the resources interconected?

Thanks,

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  • \$\begingroup\$ Sounds about right. \$\endgroup\$ – Andy aka Oct 27 '16 at 16:33
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Hierarchical netlist: Since pins of submodules are accessible, it's easier to track paths for functional debugging and timing analysis. Pins can be forced or probed in post-synthesis simulations.

Flattened netlist: Synthesis tool can optimize the circuit better. That provides better speed, area, and power. Conversely, debugging capabilities are limited.

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