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I understand that FPGAs can be used for digital glue logic on a circuit board, like NOR gates. They can also directly run AES encryption, Ethernet and Linux.

I'm not very rich and not an electronics expert. Nor do I have a posh logic analyser. I could probably put together a single board 6502 computer if I copied the code from somewhere. If I wanted to rationalise my component count of AND gates, flip flops and BCD decoders, is a FPGA feasible for my position? This is the level of sophistication I'm looking for, rather than microprocessor cores. Or, is there an alternative glue technology suitable for a downbeat hobbyist?

Supplemental:

A better question might be "what can I replace 5 OR gates, 3 Schmitts and a Divide by 10 counter with?" Thing is, I'm also factoring in the cost of the design software. A £25 development board + £5000 /seat compiler + £1000 programmer isn't much good to the poor and deprived.

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    \$\begingroup\$ A CPLD could be considered as a simpler version of an FPGA, and might be better suited to simple "glue logic" applications. \$\endgroup\$ Oct 28 '16 at 0:31
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    \$\begingroup\$ This isn't strictly speaking on topic, but it's fortunately been true for years that the industry has found it beneficial to make sure there are sub $100 boards (and a free tier of software tools to support them) on the market that one can use to become familiar with the idea and build state machine, video sequencer, simple soft CPU, etc projects. What specifically you get for that money changes over time. Make sure you are clear on how a bitstream gets transferred from your computer to the FPGA or config flash; the $50-100 boards often have that solved on board but the very cheapest may not. \$\endgroup\$ Oct 28 '16 at 0:47
  • \$\begingroup\$ I am really struggling to understand what OP is asking about or trying to say. What does it mean "to rationalize my component count and gates"? There is a big leap between "glue logic" and "running Ethernet and Linux" in FPGA. \$\endgroup\$ Oct 28 '16 at 1:20
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    \$\begingroup\$ @AliChen -- he knows that FPGAs can pack lots and lots of logic into one chip, but he only has a little bit of logic he wishes to consolidate into one package :) but didn't quite know that CPLDs were a thing. \$\endgroup\$ Oct 28 '16 at 1:50
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    \$\begingroup\$ Have fun: store.digilentinc.com/… AND hamsterworks.co.nz/mediawiki/index.php/FPGA_course AND there are plenty other more FPGA boards with lots of bare I/O for < $ \$\endgroup\$
    – Keegan Jay
    Oct 28 '16 at 2:00
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You don't need to be filthy rich to use programmable logic

In the "glue" world -- CPLDs are what you are after if you just need a small patch of programmable logic. In general, older CPLDs these days are 3.3V devices, with newer devices having 1.8V cores and 1.8 or 3.3V I/O, and can be in-circuit programmed and boundary scanned through JTAG, with the "program memory" internal to the device. (5V CPLDs existed, but are universally obsolete.)

The one downside is that they generally are only supported by a vendor-specific toolchain (such as Quartus for Altera, or ISE for Xilinx.) Fortunately, free-as-in-beer, albeit limited-size, versions are available, and they're large enough for CPLDs as well as the smaller/less expensive FPGAs that are available on not-terribly-expensive devboards these days.

Also, for FPGAs -- most of your debugging will be done at the simulation level with the aid of a testbench, as opposed to in the silicon directly. Furthermore, most FPGAs have support for internal node scan through JTAG, although the free-as-in-beer toolchains may or may not support it. Finally, some FPGA technologies require the "program" to be loaded into them at startup (Xilinx, Altera, and Atmel parts are all this way; Lattice and Actel/Microsemi parts, on the other hand, are CPLD-like in that the "program" is stored on-chip persistently.)

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  • \$\begingroup\$ The question is about FPGAs. Classic CPLDs are drastically more limited, though there are a few parts that blur the line. Using a true FPGA on someone else's board is within almost anyone's budget. But it's true that it's easier to put a simple CPLD on a custom board than a typical FPGA with its multiple supply requirements, etc. \$\endgroup\$ Oct 28 '16 at 0:53
  • \$\begingroup\$ Yes to the new intro ;-) \$\endgroup\$ Oct 28 '16 at 0:54
  • \$\begingroup\$ @ChrisStratton -- I'm addressing both because they fill different niches, really. \$\endgroup\$ Oct 28 '16 at 0:54
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    \$\begingroup\$ One big difference is that most CPLDs have the memory built-in, whereas many FPGAs are RAM-based and require an external EEPROM to store the configuration. \$\endgroup\$ Oct 28 '16 at 1:01
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    \$\begingroup\$ @SpehroPefhany -- added some notes on that \$\endgroup\$ Oct 28 '16 at 1:49
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Though not exactly answering your question, if you want to gain some knowledge/experience with digital logic design/hardware description language (HDL) on the cheap side, you can download free versions of FPGA vender tools which come with HDL simulators (Altera comes with a version of Modelsim, Xilinx has their own built in simulator in Vivado).

Basically you would write source code that you could ultimately target to a CPLD or FPGA, but instead of buying hardware and testing it, you write another piece of source code called a test bench which stimulates (in simulation) the inputs of your design. You run the simulator tools and you can monitor the outputs (which appears like a logic analyzer) and make sure they behave correctly, or even monitor internal registers/signals.

However, I will caution you that things you are capable of doing in an HDL simulation setting is not always guaranteed to be synthesizable. I would also recommend you go ahead and use the Synthesis/Build tools periodically and make sure your design is valid. Most free versions of vendor tools allow you build up to a certain size.

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Ok, after your clarification, I understand now. You need the class of devices called CPLD.

Several manufacturers offer these devices, Altera, Lattice, Atmel, Xilinx. My experience goes with Xilinx, and I would recommend CoolRunner-II. The sample development board is $37 at Mouser.com, and development tools (for basic sizes) are free, including logic simulator. You can find sample boards for under $5 on eBay.

The smallest package for CoolRunner is QFN-32 (32-pin, 5mm x 5mm chip), with 0.5mm pitch, and it goes for $1.40 in qty 1. If you are uncomfortable with QFN, they have TQFP-44, with more DIY-style pins to solder. The minimal chip has Schmitt trigger inputs, which is not common on CPLDs, 30+ configurable macrocells (flip-flops with logic around), which will let you do fairly complex state machines (sequencers) and a lot of other cool things, level translation as one, all up to 300MHz.

To program it for desired functionality you will need to learn a bit of Verilog (to describe your desired functions), what to latch, on which clock, which logic function to apply. Then define inputs-outputs, and go. The Xilinx development tool comes with Verilog/VHDL compliler and all necessary tools to partition, map, and route the CPLD. You don't need to know much about internal logic architecture if your project's logic compiles and fits into the selected CPLD. If not, then you need to do more investigations.

There are other capable CPLDs like iCE40 UltraLite Familiy, by Lattice. These CPLDs a really serious, with embedded block RAMs, about 640 LUTs for smallest chip, etc., but their packaging is out of realms for DYI, 0.35mm ball pitch, 1.4mm x 1.4mm total size, etc. And I know nothing about their development tools or costs.

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What you really need, as others have mentioned, is a CPLD. Get a development kit, it will have a breadboard type arrangement for testing. Try to use something in a small QFN or SO package, as you can get carrier boards off Ebay/electronics vendors and then solder them to your circuit or plug into a protoboard.

Get a system that has schematic capture this way you will just draw in the AND / OR / NOT / NOR gates & counters. Easy peasy!

Your CPLD device will have many more pins than you need, so bring out intermediate signal nodes to spare pins for debugging, and add LED's on spare pins too.

Most CPLD's will usually require a clock, this might add extra complication to your circuit, although a simple 4pin metal can 10.000MHz clock is fairly cheap and simple. Once you have used synchronous logic you will never look back at your prior attempts with "glitch couple logic"

For a hobbyist, trying to make something work in VHDL will make your brain explode (unless you are a serious programmer).

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    \$\begingroup\$ A huge NO on schematic capture, taking that path basically means avoiding learning how to make real use of the technology. Of course VHDL is a "no" too, anyone sane uses Verilog ;-) \$\endgroup\$ Aug 8 '20 at 14:38
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    \$\begingroup\$ I appreciate your purist approach to wanting to do it properly , but the particular hobbyist just asked "what can I replace 5 OR gates, 3 Schmitts and a Divide by 10 counter with?" If he had said he was a bored computer science postgrad I would not have recommended the schematic capture option. I did personally find the schematic capture worked very well for me as a research engineer with many irons in the fire, it was also helpful to have a schematic and timing diagram to share with other non-engineers in the team. Our "glue logic" tied a GPS, laser scanner, and gradiometer with a PC. \$\endgroup\$
    – BobT
    Aug 8 '20 at 14:56
  • \$\begingroup\$ Note I also use Labview in preference to procedural languages ( I can manage MATLAB ok), some people are just more visual, On the other hand a lot of programmers and mathematicians are very musical. An effective team combines the strengths of all team members. . \$\endgroup\$
    – BobT
    Aug 8 '20 at 15:00

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