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I am learning MIT open course 6.002 and 6.004 by myself, but met something unclear about noise margins in their materials.

In 6.002 (Electronics and circuits), the teacher gave a relation of the 4 parameters characterizing the relations of voltages and logical levels: $$V_{RL} > V_{SL}, V_{RH} < V_{SH}$$ see the slide below. (Here I used a different notation of the parameter subscripts, "R" stands for reciever side, "S" stands for "Sender" side):

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While in 6.004 (computation structures), different relations of these four parameters are given, namely: $$V_{RL} < V_{SL}, V_{RH} > V _{SH}$$ see the slide below:

enter image description here

While I don't think either one of them is wrong because they have been published for a long time, sth must be wrong with my own understanding. To me, I think the first (6.002) is more easy to understand, because the a valid input might be corrupted by noise so that a larger range in the reciever side can ensure valid input is recieved.

But according to explanation of 6.004, the second relation also seems to be right, which states that "a valid signal at the output of a device will appear as a valid at a connected device input, despite a modest amount of noise introduced by the connection", so "a combinational device must accept sloppy input representations but produce squeaky-clean representations at its output".

I am totally confused about this difference. Could anyone please give some clarifications? Thanks in advance.

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To answer your question, you are misreading the initial slide. It lists the noise margin as \$V_{OH} - V_{IH}\$ and \$V_{IL} - V_{OL}\$. The noise margin must be greater than zero, and is a measure of how much noise can be tolerated between gates to still register proper logic levels. I don't know where you got your initial equations, which are incorrect.

  • \$V_{OH} - V_{IH} > 0 \$ becomes \$V_{OH} > V_{IH}\$

  • \$V_{IL} - V_{OL} > 0 \$ becomes \$V_{IL} > V_{OL}\$

All of this talk of receiver and sender is over complicating the problem since everyone discusses these concepts in terms of input and output levels.

Keep in mind what these terms refer to:

\$V_{IL}\$ : Highest possible input voltage which will register as a low logic

\$V_{OL}\$ : Highest possible output voltage representing a high logic produced by the gate

\$V_{IH}\$ : Lowest possible input voltage which will register as a high logic

\$V_{OH}\$ : Lowest possible output voltage representing a low logic produced by the gate

Consider: \$V_{IL}\$ and \$V_{OL}\$, which describes the case of one gate producing a low output feeding into the same gate as an input.

If two gates are back to back and \$V_{IL} = 2V\$ and \$V_{OL} = 2.5V\$, or \$V_{IL} < V_{OL}\$ , the gate clearly won't work: the highest 'low' output voltage produced would not be low enough to register as a 'low' voltage at the next gate.

So the constraint is \$V_{IL} > V_{OL}\$ for proper functioning.

Similarly, you have a gate producing an output voltage \$ V_{OH} = 4V\$ feeding into a gate with \$V_{IH} = 4.5V\$. The 4V input will not be registered as a high input at the next gate, since it is less than \$V_{IH}\$.

So the constraint is \$ V_{OH} > V_{IH} \$

Typically for a robust system, you want the \$V_{IL} \$ and \$ V_{IH}\$ to be about half of the supply voltage. And for \$V_{OH}\$ to be at the positive supply and \$V_{OL}\$ to be at the negative supply. This gives you a solid noise margin of half of the supply voltage for both logic levels.

EDIT

Based on your comments there is some confusion regarding inputs and outputs. A circuit produces an output, based on its input states. It does not produce an input; inputs are driven by other logic gates. VIH and VIL are not produced by the circuit. They are simply the 'most-off' input levels (from previous gates) which will still register properly. An output will produce a logic level (VOL or VOH). This may or may not be corrupted by noise as it travels to the next input. If the noise is sufficient, it will cause the output voltage of the previous gate to change enough to register as the opposite logic value in subsequent gates.

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  • \$\begingroup\$ Thank you @jbord39 for your explanation, but I might not state my first situation clearly. I'm learning at the edx platform, and the course staff said that a valid input must get a valid output, while a valid output does not necessarily imply a valid input. So if this is the case, suppose we have $V_{IL}=2.5V$, whose output is corrupted by noise and thus resulting to 2.6V, then this would be out of the valid range of output signal if $V_{OL} = 2V$. So the valid output range should be larger than input, so as to be immunity to potential noise. So......, the staff is wrong? \$\endgroup\$ – user123 Oct 28 '16 at 4:42
  • \$\begingroup\$ An input will never drive an output. Outputs drive inputs; not the other way around. So in your example. VIL = 2.5V is the highest possible input which will be registered as a low voltage. It is not produced by the gate. It is simply the highest input the gate will still think is a low voltage. So if VOL is 2V and feeds into another gate with VIL = 2.5V; it will always work! The 2V output produced by the first gate will always be lower than the 2.5V required at the next gate to be registered as a high logic level (ignoring noise) \$\endgroup\$ – jbord39 Oct 28 '16 at 4:49
  • \$\begingroup\$ The situation you are describing will FAIL EVERY TIME WITHOUT ANY NOISE. The noise margin is a measure of how much noise can be added on top of the normal voltages for the circuit to still function properly. If VOL is 2.5V and VIL is 2V, the nominal output voltage trying to register as a low voltage will be too high for the next gate (VIL = 2V) to see as a low voltage. Before any noise is even added. \$\endgroup\$ – jbord39 Oct 28 '16 at 4:51
  • \$\begingroup\$ What I said in the last comment is just what the MIT professor said in his lecture, if I understand correctly, please wait for me to post his slide and lecture. \$\endgroup\$ – user123 Oct 28 '16 at 4:53
  • \$\begingroup\$ @David: Everyone you are quoting from your courses is correct, but your understanding is not. VIL is not produced by a gate. It is just the level at which the gate fails to register a proper low logic level. Same with VIH. Nothing makes them. A circuit doesn't make an input. A circuit's input is driven by another circuit, and its outputs respond accordingly. VIH and VIL are the input levels which describe when the outputs stop working properly. \$\endgroup\$ – jbord39 Oct 28 '16 at 4:53

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