I've to design an input stage for signal conditioning of a voltage signal coming from an high output impedance sensor. The sensor output impedance is 100k, and the amplitude of the voltage signal is 0-5mV. The frequency of the signal is between 50-150 kHz. I'd like to minimize the op-amp used in the circuit. In terms of "circuit blocks" what architecture do you suggest?
I was thinking of using a voltage buffer for the input stage, in order to have a low impedence at the buffer output and then amplify the signal with a non inverting op-amp.
Is it a good idea?
If I had to use an opamp with a small gain bandwidth product, is there a way to externaly compensate the op-amp dominant pole and increase the GBW product?
Thanks for your help!