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The glitches due to race condition can be avoided by using a negative-edge triggered flip-flop instead of the positive-edge-triggered flip-flop used.

What does this mean?

Source: http://www.zeepedia.com/read.php?the_555_timer_race_conditions_asynchronous_ripple_counters_digital_logic_design&b=9&c=26

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  • \$\begingroup\$ It is explained in the article itself. Draw by yourself waveforms and check what happens for varying timing of the first flip flop, specially in respect of the hold time of the second flip flop, and then analyze what happens if the second FF is triggered by falling edge \$\endgroup\$ – Claudio Avi Chami Oct 29 '16 at 20:16
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This is an issue when you have one flip-flop output driving the input of the next. If both flip-flops update on a rising edge, then the second one will be sampling its input at the same time the first is updating the output. If the clock has more delay (due to trace length or capacitive loading) than the signal, then the second flip-flop can miss the value. Note that this problem is independent of the clock frequency, slowing down the clock doesn't fix it, only fixing the relative delays will help.

On integrated circuits, FPGAs, and high speed interconnects, this is handled by careful clock routing and detailed knowledge of the setup and hold times of the flip flops, as well as their propagation delay. However, for low speed buses routed on PCBs, there is another solution: update outputs on the negative clock edge, and latch inputs on the positive edge. That way, there is an entire half clock cycle for the signal to stabilize before it will be read, and slowing down the clock gives more time for outputs to stabilize. SPI is a good example of a communication protocol that operates this way.

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Here are the general inequalities you need to satisfy in order to meet setup and hold requirements between a launch flop that operates on positive edge of the clock and a receiving flop that operates on the negative edge of the clock. Observe if you will, with great benefit that the hold inequality is now dependent on frequency (or the clock period), and that you get approximately half of the clock cycle time of guaranteed immunity to hold (assuming 50% duty cycle). The drawback is that you also get half a cycle less time to meet setup. But since this is typically used for slow speed interfaces, that is generally OK.

enter image description here

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The second FF being negative edge triggered prevents the hold violation that could occur (race condition) by having two same-polarity-triggered flip flops back to back.

Having the second flip flop negative edge triggered ensures that the first FF holds its value long enough to satisfy the hold time for the second flip flop (since the clock trigger arrives half a cycle later).

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In the circuit the text refers to, the and-gates are enabled at the same time the flip-flop is toggled. The means any differences in the propagation through the flip-flop appear at the output of the gates. If you use a negative edge trigger, the and-gates are disabled at the same time the flip-flop is toggled. Both and gate outputs will be zero while the flip-flop is changing. Then when the clock goes high the stable output of the flip-flop is allowed through the and gates.

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