To make it easier to read a waveform in the testbench, I want to use a signal/variable that is of string type. Basically e.g when I am reading address 0x03 from an SPI device, the string shall say that in words until the SPI transfer is complete.
This will make it easier to read the wave output.
1) String variable/signal must be given bounds when it is created. Unlike C++ it does not seem to internally expand/contract to fit what is assigned to it at run-time. This should be possible for an aggregate.
2) Cannot use (others=>'') notation with string type even though it is supposed to be an array.
3) Sometimes I have a string returned from a different function that needs to be concatenated with the msg in the testbench. If I have to enter bounds for the string when I assign it value, this will become impossible.
Is there a way to use a string without assigning bounds in VHDL? Atleast can I assign value to a string such that if my assigned string is less than max bound, the rest of the string shall be set to space characters automatically?