I've been reading Fundamentals of Digital Logic by Vranesic, and while it goes over the syntax of Verilog, it doesn't really say how to use any of the tools available for Verilog.

It seems there isn't any IDE for writing Verilog. I'm used to programming in languages such as C, C++, Java, etc. and all of these allow me to compile them with an IDE/terminal and I see an output for what I've written. I don't understand what the output of Verilog is supposed to be.

For example, lets say I wanted to write a module for an AND gate:

module andGate(x, y, z);
  input x, y;
  output z;

  assign z = x & y;


How would I know this is correct? Is there some console I can interact with, where I can apply hi/lo to the inputs and see that it actually works like an AND gate?

If there's any programs you can recommend for Linux, I'd really appreciate it. Also, I'm just a hobbyist, so I have no real reason to buy some commercial license/software.

  • \$\begingroup\$ The most practical way to see the results of your code is to put it on something like an FPGA. There are lots of entry-level hobby FPGA modules you can get for under $100 that are a good way to get practical experience with Verilog and the hardware that it is describing \$\endgroup\$
    – KyranF
    Commented Oct 30, 2016 at 5:15
  • \$\begingroup\$ Oh and using a Verilog simulator \$\endgroup\$
    – KyranF
    Commented Oct 30, 2016 at 6:24
  • \$\begingroup\$ @KyranF, any particular simulators or modules you can recommend? \$\endgroup\$
    – boy
    Commented Oct 30, 2016 at 22:51
  • \$\begingroup\$ I am doing FPGA stuff myself, so i use my manufacturer's project management/IDE and simulator package. Lattice Semiconductor have a program called IceCube2 which I use for compiling and synthesizing the code for flashing onto my IceStick USB development board. The simulation is done in a second (included) package called Synplify Pro (for RTL viewing) and also in Aldec-HDL (A-HDL) simulator. It's all very messy, I would not recommend it. Find a nicer all-in-one package like from Xilinx/Altera. \$\endgroup\$
    – KyranF
    Commented Oct 31, 2016 at 15:35

2 Answers 2


Quartus by Altera has a free "web edition" that I've been using and linked earlier availvible for both Windows and Linux. It can build for a variety of FPGAs and then comes with a built in RTL viewer which is a good way to visualize you netlist. If the RTL viewer isn't enough, ModelSIM (which comes with Quartus) allows you to force inputs and simulate outputs.

Your example code compiles correctly and the built in RTL viewer shows the following image (an and gate):

RTL viewew AND gate


The output of Verilog code is a circuit that has inputs and outputs just like any normal program. The difference is that the order of lines of code may matter, or may not matter. Some lines of code run in parallel, some sequentially, some in-between. Learning to read music scores helps.

HDL IDEs come from the vendor. EDA Playground comes the closest to the Visual Studio, Eclipse, ipython, ijulia type of IDEs you have experienced. EDA Playground's problem is that vendors have extended standards, and implemented a subset of the standard. Some FPGA vendors don't guarantee backward or forward compatibility. The "test" part of EDA Playground is really a logic test, not a test that guarantees the ability to synthesize (work with a vendor's hardware).

FPGA vendors have much better (and free) IDE's that capture a more complicated workflow than what is experienced when writing C, C++, Java, etc. For example, Xilinx Vivado has constraints, clock domains, and exception lists in their workflow. The concept of testing in this world is "test to get it to work", not pass a unit test that can fit into version control, publish system.

FPGA vendor IDEs are overwhelming at first. But from a traditional programming point of view, Xilinx Vivado is very good. It underlines syntax errors as you type. Blue and yellow bars indicate code that has problems. Mouse over pops up a window with occasional suggestions. File saving is prompted before you accidentally lose edits.

The biggest problem is engineers don't think about gates anymore when designing circuits. Engineers work at a Verilog abstraction level called RTL and "behavioral." The IEEE 2017 System Verilog has over 1300 pages documenting this.

Most textbooks start at the gate level and document gate-level design strategies of the 1980's. In the FPGA programming world, gates are used by the software to explain what is right or wrong with your code. And most vendors immediately translate everything into a very tiny subset of the 1970's gate design world that includes XOR, MUX, LUT, D flip-flops. You need to start with a course that drives you into a specific vendor's documentation. The FPGA market is changing too fast to expect a harmonized Verilog standard; interpreted and implemented in the same way across all vendors.


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.