Made from sufficiently fast gates, asynchronous counters count perfectly, even at high frequencies. Its just that you will have some difficulties reading the current count.
Each more significant bit changes later than its preceding less significant bit. Given enough bits, and enough frequency, it can happen that the LSB update of the next clock happens before the MSB update of the previous clock. In this case, at no time the but pattern at the output is guaranteed to match the count - but if you stop clocking, the bits will eventually settle to the right pattern, so I am hesitant to claim that the counter didn't work, i.e. count, the whole time.
When working at low frequencies, you can decode the counter output of an asynchronous counter using conventional logic, it will "just" produce erratic results for the short time the counter "rattles the bits". If you ignore this glitch on the output, everything works. With increasing frequency, the "short glitch" starts becoming longer compared to the clock period, and at some point you can't just "ignore the minor glitch" anymore. That's where the latch helps: You delay passing the counter output to the next stage until all bits have settled, and pass them all at once then.
Obviously, in the extreme case depicted in the beginning of the answer, where there is no point in time you get all bits right, a simple latch can't help anymore, but multiple staggered latches might do the job.