# How does the clock skew affect the design?

What does these statements explain with respect to setup and hold time, I am unable to understand:

If combinational logic delay is very short or clock skew is large enough then output of 1st FF would change (hence input of 2nd FF is changed overriding the previous input) before HOLD time condition for the input of 2nd FF is satisfied and hence circuit would not work properly due to this HOLD TIME violation. Or input of 2nd FF change to create SETUP time violations.

The input to D must not change for a minimum time after the clock. This is the hold time. It also must have stop changing a minimum about time before the clock. This is the setup time. If the input flip-flop is clocked slightly before the output flip-flop, the second D may be changing in the setup hold time window. This can cause erratic operation.

Here's a more thorough explanation of this circuit Setup and Hold requirements. If you want to meet setup and hold requirements at the receiving Flop, you will generally need to meet the following inequalities. Observe, that setup requirement is dependent on the cycle time, which means that if you violate setup, one solution would be to increase the cycle-time until you stop violating. But for hold, there is no dependency on cycle time (for rising-edge to rising-edge circuit) since hold will be checked using the same clock edge (rising edge in this case). for more info please also see my answer for rising-edge to falling-edge circuits at: Why do we use negative edge trigger Flip Flop instead of positive edge triggered?

You will need to study the following: Timing for DFF and Clock skew.

What this passage says is that second flip-flop, to latch data on its D input properly, should have logical value at its input be constant some time before and after clock activates its latching.

It details two scenarios:

• combinational circuit is too fast [low Tcd]. It means that when clock is rising (or falling - depending which edge is used by DFF), if this circuit is too fast output of previous DFF will appear within the time when second DFF should have its input D stable for its proper operation. If it happens, this second DFF's output is not guaranteed to be valid;
• the same situation, but relative to clock's skew - clock may arrive later to second DFF, or clock may have slope which will trigger it later than first DFF, and thus violating condition that second DFF's input should be stable before latching starts and some time after it starts.

If there's timing violation for DFF, trigger's output validity is not guaranteed, and thus whole circuit may fail due to one small simple DFF.