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I have a board which has many of the same IC MAX9611. According to the datasheet it should be bypassed by parallel 0.1uF and 4.7uF caps. Now I have like 15 of these right next to each other:

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I am not sure if I need to solder all these caps for each and every IC. For one, maybe the capacitance of my 2 layer board (VCC pour top, GND bottom) will go to high and it maybe interfere with I2C signals? I have no experience with this configuration so I do not know what will happen in the worst case scenario... please shed some light!

I will read/write to each IC individually, so no 2 IC will be operational at same time.

I mean do I need to solder all the caps, or I can e.g. get away with having caps for each 2nd chip?

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  • \$\begingroup\$ Well, when the datasheet says one IC should have 4.7µF and you sahre it between a dozen ICs, does then every IC still have 4.7µF ? \$\endgroup\$ – PlasmaHH Oct 31 '16 at 10:18
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    \$\begingroup\$ Do they switch at the same time? If not, you can do creative things given that the impedance from capacitor to the IC is still low. If they do switch at the same time, you are in a worse situation. Simulate the event with all parasitics, ESR, ESL and trace inductance in particular and you will see how it looks. \$\endgroup\$ – winny Oct 31 '16 at 10:24
  • \$\begingroup\$ @winny no I will read/query each IC individually so they do work/switch at the same time \$\endgroup\$ – Sean87 Oct 31 '16 at 10:25
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    \$\begingroup\$ You only need to bypass the ones that you want to work properly. \$\endgroup\$ – Olin Lathrop Oct 31 '16 at 11:07
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    \$\begingroup\$ @OlinLathrop I take that as I need to bypass all :P :D \$\endgroup\$ – Sean87 Oct 31 '16 at 13:20
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The datasheet is written from the perspective of one chip. When you have multiple chips you can begin to take liberties.

A general rule of thumb that I work to is to have one 0.1uF bypass capacitor right next to the power pins of every device (some designs also call for a 0.01 as well). That is non-negotiable. Then each group of three or four chips has a larger reservoir capacitor of say 10uF with it.

The 0.1uF (and optional 0.01uF) handle the high frequency transients of clocks and such, and the larger 10uF handles any larger switching demands from the group of chips.

So for your design of 15 chips you could have 15 x 0.1uF and 5 x 10uF. That's 10 less capacitors.

How you arrange the traces for the power also has an effect. In general you want the power plane to connect to the reservoir capacitor and then feed the bypass capacitors from that capacitor rather than direct from the power plane. That way they get decoupled by that capacitor and don't just (largely) ignore it.

The selection of the reservoir capacitor isn't as critical as you would expect since you aren't using all the chips at once. Better to go above what they say for one chip, but you don't need as much as three times (though you could). You want more than 4.7 though since if one chip should need most of that there'd be nothing left for the next chip and (depending on power impedance) you may find it's not got the power in the capacitor for you.

One further advantage of this kind of arrangement where you end up with less overall capacitance, besides saving space, is that your total power supply capacitance is reduced. That means less inrush current, which can be a big factor when working with current limited supplies with strict regulations on how much inrush you can have, such as USB.

When you do start having lots of power supply capacitance for many many chips like this you might also want to consider a power supply system with a soft start option to reduce your inrush current and charge all the capacitors more slowly. Hold any active portions of the circuit in RESET until the "power good" output of your soft start regulator becomes active.

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    \$\begingroup\$ If two devices won't be switching simultaneously, neither would have any more objection to supply voltage transients when they're not switching than when they are, and if a bypass cap shared between the two devices was just as close to each device as an unshared cap would be, what disadvantage would there be to sharing caps in such fashion? \$\endgroup\$ – supercat Oct 31 '16 at 20:56
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    \$\begingroup\$ @supercat Since all the devices (appear to) share a single I2C bus they will all be doing things even passively (reading the I2C stream and looking for their address). They want their HF cap to handle the transients from working with that clock, but the LF cap to handle the larger, slower, transients whilst operating. So even though only one chip may be actively in use at a time all 15 chips will be monitoring that I2C bus, which is an active operation and requires decoupling. If the chips were completely disabled then you could get away with less decoupling, but they aren't. \$\endgroup\$ – Majenko Oct 31 '16 at 21:06
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The most important point is that the .1μF capacitor is connected with really low impedance to each chip. If your GND pour on the bottom is making a really good ground plane, you are likely to get away with one small cap per two ICs, if you orient the VCC pins of those ICs to be really close to each other and the bypass cap, and have ground vias near the GND pins of both ICs and the bypass cap. But hey, both ICs get the same I2C clock signal, so they draw current at the same time, so you likely need a bigger cap if it bypasses two chips. I would not go below .15μF in this case.

I agree with Majenko on the bigger reservoir caps.

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  • \$\begingroup\$ I agree with this for the most part... check the IC's data sheet and see if they specify a maximum distance for the 0.1uF cap (I saw one where it said they should be <0.5" from the chip). If you can put one cap between two chips and stay within that distance, you're good to go. I do disagree with increasing the size of the smaller bypass cap though -- increasing its size reduces its frequency response, and it's important to have an appropriate frequency response for a bypass cap to do its job. \$\endgroup\$ – Doktor J Oct 31 '16 at 14:37

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