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In the datasheet for the DAC8812, there is this diagram in Figure 33:

enter image description here

What is the point of drawing cascading inverting buffers when, logically, it's the same as a single non-inverting buffer? This isn't the only place I've seen it.

edit: This is different than the question here (Why two inverters cascaded in multiplexer control signal terminals?) because I'm asking about an equivalent logic diagram, not physical logical circuitry. And in the diagram in question, there is no pick-off between the buffers.

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    \$\begingroup\$ I reckon that's a more physical description of what's going on, rather than the logical version you appear to want. That means it's been drawn by the chip designers, rather than by the customer-facing applications engineers. Much the same as my wife and I will go to look at a new car, I'll be asking whether it's 2 or 4 valve per cylinder, and she wants to know what colours are available. \$\endgroup\$ – Neil_UK Nov 1 '16 at 21:12
  • \$\begingroup\$ @IgnacioVazquez-Abrams - your accepted answer to that question doesn't really explain this one since this one doesn't use the 'intermediate' inverted signals \$\endgroup\$ – brhans Nov 1 '16 at 21:12
  • \$\begingroup\$ Should be indication of (a) internally buffered signal and (b) internal delay? Two NOT gates are implemented as buffer (as I recall NOT+NOT in series is the right way to implement non-inverted buffered signal) \$\endgroup\$ – Anonymous Nov 1 '16 at 21:15
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    \$\begingroup\$ Possibly because you can't get inverting and non-inverting buffers in the same package, so it assumes you're using one chipload of buffers; since the circuit needs one inverter, they drew the rest of the buffers as the same type? \$\endgroup\$ – Ian Bland Nov 1 '16 at 21:20
  • \$\begingroup\$ Cascaded inverters are so commonly used in HCMOS gates that it is considered the norm. For example, a single (one-of-six)74HC04 inverter consists of three cascaded inverters. However, a 74HCU04 is the special case of a single-gate inverter (often used in oscillators). Some lazy chip-makers don't bother stating that their logic is "buffered" - meaning that they're using cascaded gates. \$\endgroup\$ – glen_geek Nov 1 '16 at 21:21
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There is no reason to do this, other than the picture was drawn by some technical writer from a gate design documentation provided by a designer. The reason is that there is no such thing as non-inverting buffer, a pair of basic CMOS transistors forms an inverting circuit, so an non-inverting function must be made out of two inverting gates in sequence.

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