Now what does time selectivity actually means here?
I take it as implying that at higher carrier frequencies, the speed of time division duplexing is also enhanced but, I'm not convinced that TDD does actually benefit much because, in FDD (frequency division duplexing), a higher carrier frequency also means a faster synthesizer lock time....
For a frequency synthesizer's PLL (phase locked loop) to lock, it needs to determine an "error" so that it can drive to the right frequency. That error is the difference between where the output frequency currently is and, where it needs to drive to (the target). Clearly, if the target frequency is higher, the error is "calculated" more often and this can "drive" the feedback loop more regularly and obtain lock more quickly. Take a look at this: -
There are three responses. The slowest has a loop bandwidth of 1 kHz and the fastest has a bandwidth of 20 kHz. For a low target frequency you need to have a low loop bandwidth so that the error (the signal that drives the VCO) does not contain significant ripple artefacts that can cause frequency jitter when locked.
Hence, if the target frequency is high, the loop bandwidth can be high for the same jitter as the low target frequency. A high loop bandwidth is quicker at responding as per the picture above.
Maybe ultimately the claim about TDD benefiting when higher carrier frequencies are used will be reset by changes in technology (beneficial to FDD) which we are not yet aware of.