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As I checked some documents about library ieee.std_logic_arith it seems resulting length of A+B will be 64-bit when both A and B are 64-bits.

I want to know if ieee.std_logic_arith have an add operator which generates carry (so that operator generate 65-bit output for adding two 64-bit operands)?

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    \$\begingroup\$ ieee.numeric_std will provide a result the length of the left operand. You could concatenate a leading sign bit or zero bit (for unsigned) with the left operand to produce your 65 bit result. A look through the source for Synopsys' std_logic_arith shows it's "+" does the same thing. \$\endgroup\$
    – user8352
    Commented Nov 3, 2016 at 9:52
  • \$\begingroup\$ Please do not use the ieee.std_logic_arith library. It is outdated and makes problems when combining with others. \$\endgroup\$
    – Botnic
    Commented Nov 3, 2016 at 10:32
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    \$\begingroup\$ I suggest you to use std_numeric library instead of arith... You can see some details here: userweb.eng.gla.ac.uk/scott.roy/DCD3/05_Arithmetic.pdf \$\endgroup\$
    – ferdepe
    Commented Nov 3, 2016 at 10:41
  • \$\begingroup\$ @Botnic So you suggest using std_numberic? And besides, can you name some of std_logic_arith problems or provide a link about this? \$\endgroup\$
    – VSB
    Commented Nov 3, 2016 at 10:54
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    \$\begingroup\$ Please read: tams.informatik.uni-hamburg.de/vhdl/doc/faq/FAQ1.html#4.11 \$\endgroup\$
    – Botnic
    Commented Nov 3, 2016 at 11:01

3 Answers 3

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ieee.numeric_std will provide a result the length of the left operand. You could concatenate a leading sign bit or zero bit (for unsigned) with the left operand to produce your 65 bit result.

A look through the source for Synopsys' std_logic_arith shows it's "+" does the same thing.

Library ieee;
use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
use ieee.std_logic_arith.all;

entity adder65bit is
    port (
        a,b:    in  unsigned(63 downto 0);
        carry:  out std_logic;
        sum:    out unsigned (63 downto 0)
    );
end entity;

    architecture foo of adder65bit is 
    signal temp:  unsigned(64 downto 0);
    begin
        temp <= '0' & a +  b;
        sum <= temp (63 downto 0);
        carry <= temp(64);
end architecture;

You didn't specify signed or unsigned, this is unsigned, the operands and the results can be ether signed or unsigned instead.

This code analyzes, elaborates and simulates. It works be setting the left operand to be 65 bits long. You mentioned carry so it's shown with one in a method compatible with earlier VHDL tool implementations.

Note the "&" and "+" operators have the same priority, they will be executed in the order they are found left to right.

adder65bit_tb.png

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The result length is the same as left operand lenght. So, you have to consider how many bits will have the result in order to declare the addends. No carry is generated.

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I would suggest you explicitly left sign-bit extend (signed) or left zero-bit extend (unsigned) your inputs by 1 bit. This will ensure you retain the carry bit, but it will also make it clear to the future reader of your code that you are specifically keeping the carry. I would further suggest putting comments describing your intent to do so.

Even if you could do it implicitly, I would still suggest you do it explicitly just so the user doesn't have to traverse your file(s) to determine if the size of the output vector is the same or 1 larger than the inputs.

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