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I'm not quite sure how external interrupts will work with several peripherals on the same EXTI line.
For instance, if I configured interrupt on line X and on the same line(of course another GPIO port) I have SPI MOSI or SCK, or maybe ADC working, would I receive interrupt every time one of these pins was triggered? And if I do then is it possible to get information about what pin was actually triggered?
Thanks.
When using a GPIO pin for external interrupt (without setting the alternative function for the pin) you can have exactly one interrupt per line. Hence, you can never have an external interrupt for both PA6 and PB6 since they are located on the same line.
However, when you are activating the alternative function for a pin as you would do for SPI and other peripherals you will get the interrupt from the peripheral itself (i.e. another interrupt vector).
You can not configure a pin as both alternative function and as a GPIO pin (with external interrupt).
I/O ports on the STM32F10x are organized into 7 groups of 16, designated PA0, PA1, ...PA15, PB0, ... up to PG15. Typically, only a subset of these are brought out to pins.
To trigger an interrupt, a port must be configured in Input mode.
PAx, PBx, ...PGx (x=0..15) are muxed into External Interrupt Line x, so only one of these ports drives Line x. That port is selected by the EXTIx bit field in the AFIO_EXTICRy (y=1..4) register. The other ports on Line x are ignored as far as external interrupts are concerned.
Line x is unmasked by writing a '1' to the appropriate bit in the EXTI_IMR register, and rising and/or falling edge trigger is selected in the EXTI_RTSR and EXTI_FTSR registers.
For example, to have an external interrupt on PC4 rising, set the EXTI4 bits in the AFIO_EXTICR2 register to (binary) 0010 to select port PC4. Write a '1' to the MR4 bit in EXTI_IMR to enable Line 4, and to TR4 in EXTI_RTSR to select rising edge. (In this case, PA4, PB4, and PD4-PG4 are not available as external interrupt sources.)
The EXTI_PR register can be read to determine which lines have pending interrupts.
The NVIC must be configured to accept and process the interrupt request. External interrupts 0 through 4 have individual interrupt vectors, but 5 through 9 share one vector, as do 10 through 15.
