According to the datasheet:
When writing serial data to the Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P, data is clocked on the rising edge of SCK.
When reading data from the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P, data is clocked on
the falling edge of SCK. See Figure 27-12 for timing details.
-- ATMega324PA Datasheet section 27.8.2
And Figure 27-12 is:
That looks like CPOL=0 / CPHA=0 to me (SPI Mode 0):
For CPHA=0, data are captured on the clock's rising edge (low→high transition) and data is output on a falling edge (high→low clock transition).
Mode 0 and Mode 3 look like they should be interchangeable because they both end up clocking in on the rising edge and clocking out on the falling edge of the clock. However the difference comes when you start doing a transfer - with Mode 0 you start with a rising edge (clock in) and then get a falling edge (clock out), whereas in Mode 3 you start with a falling edge (clock out) followed by a rising edge (clock in). So although you get the same data clocked in to the chip you may find reading the data becomes offset by one bit depending on how you actually do the reading.
It may in fact be that the programmer you have is really working in Mode 0 but during times of zero activity it places the clock and data pins into a high impedance state with pullup resistors to allow bus sharing. That would look like "idle clock high" when it isn't. When programming starts it first places the pins in output mode and pulls the clock low to start the SPI sequence with a LOW clock signal (Mode 0).