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UPDATE:
How to measure (/make a good approximation of) parasitic inductance of a lead frame of a chip package?

This parameter is very important at high frequencies (1GHz and more) because it affects power integrity. E.g. 10 mA current at 1 GHz flowing through 1 nH parasitic inductor causes voltage oscillation of 63 mV amplitude. Any additional 1 nH of parasitic inductance adds substantial power fluctuations (and it can't be bypassed by a capacitor, 'case inside the chip's package).

So, it would be nice to know how it can be estimated or measured.

I may simply rely on the manufacturer's figure (to be put into my simulator), but would be safer to double check it.

Addendum

Original title: how possible: inductance without specifying loop

Original question:

I came across multiple examples when inductance (usually parasitic) is reported without specifying a current loop.

Two examples:

  1. MOSIS bond wire electrical parameters (URL, paragraph 14): "Inductance of 1 mil gold wire of 2 mm length is 2 nH".

  2. Formula for ESL (equivalent series inductance) of capacitors by Murata, URL:

enter image description here.

In the both examples a loop was not specified.

How can they report inductance (ratio of magnetic flux though some contour to current) of something without specifying the loop (contour) first?

PS: Likely they assume some "typical" current return path but if so, it would require specifying additional parameters (e.g. for bond wire parasitic inductance one needs to know PCB stackup heights, distance between chip's power and ground pins, etc. to draw the loop).

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  • \$\begingroup\$ These specifications are for an element of a circuit, not the whole circuit. Therefore to make the measurement, you would need an empty loop, and loop + DUT. Component values are anyway an approximation. \$\endgroup\$ – Sean Houlihane Nov 3 '16 at 12:29
  • \$\begingroup\$ I am not sure what you mean by "specifying a current loop" means. Everything has inductance, there is no need to specify it for any current. \$\endgroup\$ – PlasmaHH Nov 3 '16 at 12:29
  • \$\begingroup\$ A string formed into a loop has inductance yet there is nothing conductive about it - it's to do with space (area) and shape. \$\endgroup\$ – Andy aka Nov 3 '16 at 12:36
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    \$\begingroup\$ @SergeiGorbikov: then you are facing a whole industry that is seeing it differently. There are even manufacturers that sell components they call inductors that have inductance values independently of the current or current return path. If you see it from the EM point of view, the return path has inductance too, and both have mutual inductance components, but usually they are orders of magnitude further away so they are negligible; all that is left to consider then is self inductance of the element at hand. \$\endgroup\$ – PlasmaHH Nov 3 '16 at 13:47
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    \$\begingroup\$ There's such a thing called partial inductance which is excactly what you are talking about: inductance definition without any loop defined. However it is still a lumped elements approximation, as said, s parameter characterization is mandatory when circuit physical dimensions approach wavelength \$\endgroup\$ – carloc Nov 6 '16 at 9:18
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Without doing a full FEMM, using '1nH per 1mm of length' is much better than assuming it's zero. It also allows you to sanity check any figures you've been given by the manufacturer.

Fortunately, as the geometry effects vary as the log of size ratios, and size ratios tend to only have a small usable range for typical ICs, this formula is surprisingly good for the typical geometries that we encounter in IC lead frames used above a ground, with wire diameters and spacings in the 0.1 to 1mm range.

Please note the use of the words 'tend', 'sanity check' and 'better', which imply a ball-park, rather than precision.

It's important to understand the limits of applicability of the inductance model. 'Extra inductance due to bond wires/lead frame' is a loose low frequency model, which in many circumstances is good enough to improve significantly over ignoring the effects. At the frequencies where we have to worry about 'extra inductance', the physical length of the electrical path from the pad to the die forms a transmission line with respect to ground. For a better model, closer to reality than the extra-inductance model, we would take the S-parameters of the die, and of the bond wire/lead frame/package, and combine them to give the S-parameters of the packaged-die, which would then be put into our board level simulator.

Extra-inductance is a loose model, as it specifically ignores the physical length, which as the frequency rises, quickly makes the model completely invalid. If you want to be picky about exactly where the inductance is measured from for the extra wire, then you have lost the license to use this loose low frequency model, and should really be using the more accurate S-parameters.

While the distance above ground does of course matter, and while whether you measure estimate the inductance from end to end or in a small loop matters, it does not matter at the level of this loose approximation. Attempting to define inductance as the delta V over a finite length of conductor due to current changes is much the same as arguing whether the angels dancing on the head of a pin are wearing M&S or Primark, it is over-interpreting the model.

As a matter of practical procedure, the way lead frame inductance is estimated is to measure the S-parameters of a packaged calibration die, de-embed the S-parameters of the lead, and convert that to an equivalent best fit added inductance that gives similar asymptotic results when used in a simulator at low enough frequencies.

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  • \$\begingroup\$ +1 Neil, thanks for sharing your experience, helpful, indeed. As I see, your ballpark estimates are for QFN. Maybe you know, does using BGA instead of QFN help in reducing the inductance and how much? \$\endgroup\$ – Sergei Gorbikov Nov 3 '16 at 15:13
  • \$\begingroup\$ Also, Neil, does the parasitic inductance depend on the distance between the package and the PCB's ground plane? We (PlasmaHH and me) had a small dispute in comments on this. \$\endgroup\$ – Sergei Gorbikov Nov 3 '16 at 15:20
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    \$\begingroup\$ @SergeiGorbikov, This ap-note doesn't answer your question about measuring, but does address the connection reactances of various packages (including BGA and micro-SMD): ti.com/lit/an/snoa405a/snoa405a.pdf \$\endgroup\$ – glen_geek Nov 3 '16 at 15:41
  • \$\begingroup\$ @glen_geek thanks a lot, good reading and right about the question addressed. \$\endgroup\$ – Sergei Gorbikov Nov 3 '16 at 15:49
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    \$\begingroup\$ @SergeiGorbikov updating my answer to address the 'distance above ground' thang. \$\endgroup\$ – Neil_UK Nov 3 '16 at 16:10

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