How to measure (/make a good approximation of) parasitic inductance of a lead frame of a chip package?
This parameter is very important at high frequencies (1GHz and more) because it affects power integrity. E.g. 10 mA current at 1 GHz flowing through 1 nH parasitic inductor causes voltage oscillation of 63 mV amplitude. Any additional 1 nH of parasitic inductance adds substantial power fluctuations (and it can't be bypassed by a capacitor, 'case inside the chip's package).
So, it would be nice to know how it can be estimated or measured.
I may simply rely on the manufacturer's figure (to be put into my simulator), but would be safer to double check it.
Original title: how possible: inductance without specifying loop
I came across multiple examples when inductance (usually parasitic) is reported without specifying a current loop.
MOSIS bond wire electrical parameters (URL, paragraph 14): "Inductance of 1 mil gold wire of 2 mm length is 2 nH".
Formula for ESL (equivalent series inductance) of capacitors by Murata, URL:
In the both examples a loop was not specified.
How can they report inductance (ratio of magnetic flux though some contour to current) of something without specifying the loop (contour) first?
PS: Likely they assume some "typical" current return path but if so, it would require specifying additional parameters (e.g. for bond wire parasitic inductance one needs to know PCB stackup heights, distance between chip's power and ground pins, etc. to draw the loop).