To compensate for my blindness here's a partial truth table: -
Please note that you have to invert R (and Q) to realize the actual truth table in the question.
Picture stolen from here!
Now that I've studied it a bit more I can see that it is derived from a the standard NAND latch: -
If you apply De Morgan's rule to the top NAND you get this: -
So, the TT is very close to that of a NAND latch.
0--0--0--1... if H=0 then SET P=1 and this is latched even if H=0 to 1
0--1--x--x... inputs are inactive and QP have latched previous states
1--0--1--1... if R=1 then SET Q=1 and this is latched even if R=1 to 0
So it is simply a variation of an SR latch with one active low input=H and one active high input=R
and that's the Truth Table for an asynchronous Flip Flop or "Latch"