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How can I find the truth table of this HR-latch? enter image description here

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  • \$\begingroup\$ Google? Logic thinking? Can you find the TT when that one inverter is not present? \$\endgroup\$ – Wouter van Ooijen Nov 3 '16 at 13:44
  • \$\begingroup\$ if I could find it in google, I will not post it her :) \$\endgroup\$ – fa6ma Nov 3 '16 at 13:49
  • \$\begingroup\$ HR FF?? Never heard of it.. Some exercise-specific beast. \$\endgroup\$ – Eugene Sh. Nov 3 '16 at 13:51
  • \$\begingroup\$ First hit: google.co.uk/… and by the way, without the gate outputs being inverted your circuit won't work so it's a -1 for effort. \$\endgroup\$ – Andy aka Nov 3 '16 at 13:52
  • \$\begingroup\$ @Andyaka there's a twist in the question: one gate is a OR, the other is a AND. This doesn't show up in a google search... Maybe because it isn't actually very useful, I don't know. \$\endgroup\$ – dim Nov 3 '16 at 13:54
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To compensate for my blindness here's a partial truth table: -

enter image description here

Please note that you have to invert R (and Q) to realize the actual truth table in the question.

Picture stolen from here!

Now that I've studied it a bit more I can see that it is derived from a the standard NAND latch: -

enter image description here

If you apply De Morgan's rule to the top NAND you get this: -

enter image description here

So, the TT is very close to that of a NAND latch.

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enter image description here

.R--H--Q--P.

0--0--0--1... if H=0 then SET P=1 and this is latched even if H=0 to 1

0--1--x--x... inputs are inactive and QP have latched previous states

1--0--1--1... if R=1 then SET Q=1 and this is latched even if R=1 to 0

1--1--1--0...

So it is simply a variation of an SR latch with one active low input=H and one active high input=R

and that's the Truth Table for an asynchronous Flip Flop or "Latch"

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