# FPGA SDC timing constraints, understanding output delay

I'm having a little bit of trouble understanding the timing convention of an SDC command:

set_output_delay 1.0 -clock_fall -clock CLK2 –min {OUT1}
set_output_delay 1.4 -clock_fall -clock CLK2 –max {OUT1}


Does this mean that after the launch clock (CLK2 falling edge), the output signal (OUT1) is allowed to transition between these min/max windows (signal edge occurs somewhere beteen 1.0 ns and 1.4 ns after the falling edge of CLK2)?

So is it basically the inverse of describing where a signal will needs to be valid: where it is allowed to transition/describe where the signal can be invalid?

Is my understanding correct?

No, these constraints don't mean that OUT1 has to transit in that timing window. The output delay is modelling the delay between the output port and an external (imaginary) register.

Delay of the path through OUT1 can be thought as follows.

t_total_delay = t_clk-to-Q + t_comb_delay + t_output_delay - t_clk_skew


The maximum value of t_output_delay (1.4 ns) is simply used for setup time and the minimum value (1.0 ns) is used for hold time.

Let's think about setup time. OUT1 has to transit 1.4 ns before (or earlier) the falling edge of CLK2. Say your clock period is 10 ns and the source register is also negedge triggered. In case t_clk_skew is zero, t_clk-to-Q + t_comb_delay has to be lower than or equal to 8.6 ns (10-1.4) to be able to meet setup time.

For hold time, t_total_delay has to be greater than zero. The critical part here is the clock skew. If t_clk_skew is very small, it is very easy to meet hold time. Even only t_clk-to-Q is usually greater than library hold time, however we don't need library hold time here, because the path is not going to a real register.

If we want to consider that library hold time, we can set a smaller output delay. It is also very common to set a negative value to be on the safe side. For example:

set_output_delay -1.0 -clock_fall -clock CLK2 –min {OUT1}

• Great answer; would you mind adding how -min affects hold time? This answer is concise and correct; with a minor edit it would be complete and be able to help a lot of people. – akohlsmith Nov 8 '17 at 16:25
• @akohlsmith I modified the answer, I hope that is helpful. I also added clock skew, because hold time cannot violate if we ignore clock skew. – ahmedus Nov 9 '17 at 11:22

That's not necessarily an incorrect way to think of it but it isn't the full explanation either. What you're really specifying are the minimum and maximum routing delays within the device from the final register data output to the external pin. This has couple uses:

1) It gives you some control over setup/hold windows at the output. Useful sometimes for troubleshooting weird timing issues. 2) More commonly, it lets you adjust the relative propagation delays between multiple synchronous signals to correct for unequal trace lengths on the PCB. This is to ensure they all arrive at the destination at the same time.

Note that you can do the same thing on input signals for the same reasons.

• So if the constraint says -min value is 1.0, and -max value is 1.4, does this means that after a clock edge at the final destination register, the final destination register's input data will NEED TO transition at some time between 1.0 and 1.4? Again, the inverse of indicating when the data needs to be valid/stable? Is the positive convention always "to the right of the clock"? I'm a little confused on which positive/negative convention to use when the data-valid-window needs to be center aligned with the clock. – user2913869 Nov 4 '16 at 13:33
• It has no impact on the final destination register's input. That setup/hold timing is fixed and known by the tools, and it'll use your specified clock period to make sure the routing delays are within spec. This only specifies the min and max routing delays from the final register's output to the output pin, and from the input pin to the first register's input. – Chris Iversen Nov 5 '16 at 16:25