# Design an AND gate using 2:1 multiplexor

I just started my computer architecture course and I'm trying to figure out universal logic, using multiplexors to represent logic blocks. I found this one example how to use a 2:1 multiplexor to represent a AND, but I could use a bit more clarification. I have truth tables from both a 2:1 multiplexor and a AND block in front of me, but can't connect the dots. sel in0 in1 out
0   0   0   0
0   0   1   0
0   1   0   1
0   1   1   1
1   0   0   0
1   0   1   1
1   1   0   0
1   1   1   1


In the circuit shown, in0 is hardwired to 0, so we don't care about any rows in the truth table where it's 1. Let's delete them:

sel in0 in1 out
0   0   0   0
0   0   1   0
1   0   0   0
1   0   1   1


Now we don't need the in0 column so it can be deleted. Also, rename sel and in1 to the inputs we've wired to them:

B   A   out
0   0   0
0   1   0
1   0   0
1   1   1


...which is just the truth table for an AND gate.

• thank you so much, I get how to go from one to the other now. any idea how to combine 2 systems? I think given tis and an inverter represented by a 2:1 mux i could make a NAND gate. – jfisk Feb 17 '12 at 2:57

Best way to look at it is to go through each possible output while changing A and/or B

Start looking at it as a multiplexer (since that is what it is).

When B is 0 the output is 0, when B is 1, the output is A

So when it the out put equal to 1? The only time it can be 1 is when B is equal to 1 since when B is 0 the output is 0. So B is 1, and the output is equal to A, if A is 0 then output is 0, and if A is 1 then output is 1!

So the only time when the output is 1 is when both A and B are 1 else the output is 0, this is the same as the output for an AND gate!

I hope this helps :D

Theran's suggestion to use truth tables is a good one. One thing to beware of with multiplexers, though: the fact that a truth table suggests a certain logic function does not always mean a multiplexer circuit will behave exactly like that function. A multiplexer where input 1 is tied high, input 0 is tied to A, and the select input is tied to B, will output a high when A is high and B is low, or when B is high and A is low, or when both A and B are high, but that doesn't means it output will always be high when A is high, nor when B is high. It's entirely possible that if A sits high and B changes state, the output might momentarily go low. This behavior is referred to as a "logic hazard". Some multiplexers include circuitry to avoid them (e.g. by ensuring that when both A and B are high, the output will be high independent of the control input) but some do not.