What's the meaning of wire [a:b] c? Is it different from wire [b:a] c? or does Verilog consider them equal? Is there any syntax to convert different arrays to each other?


1 Answer 1


what's the meaning of wire [a:b] c??is it different from wire [b:a] c

Verilog does not assume the Endianness of buses.

For example

wire [7:0] C; //Little endian [7] [6] [5] [4] [3] [2] [1] [0]
wire [0:7] D; //Big endian    [0] [1] [2] [3] [4] [5] [6] [7]

In order to select the Most significant bit of C, you need to reference C[7]. While in order to to this for D, you need to reference D[0]

If you are trying to connect two busses together in Verilog they are connected MSB to MSB and LSB to LSB

So in the above example if we are trying to connect C and D together the LSB of C which is C[0] will be connected to the LSB of D which is D[7]

If C and D are not the same length

wire [7:0] C;
wire [0:3] D;

When you try to connect them together in Verilog they are connected starting from the LSB

In this case;

C : [7] [6] [5] [4] [3] [2] [1] [0]


D : ....................[0] [1] [2] [3]

C[0] => D[3]

C[1] => D[2]

C[2] => D[1]

C[3] => D[0]

verilog considers them equal?

Well they are both multi-bit wires there is no difference between them

how to use it??

Just don't connect big-endian to little-endian unless you really mean to do this. Otherwise this might not give you the results you expect

  • 1
    \$\begingroup\$ It's about the same in VHDL. You can create vectors with the notation std_logic_vector(7 downto 0) or std_logic_vector(0 to 7). This will determine the order of the bits. \$\endgroup\$
    – lucas92
    Nov 4, 2016 at 13:54

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.