Clocks are perfect for AC termination, because they are DC-balanced / and (hopefully) always at a 50% duty cycle. If yours (assuming a CMOS clock) is long enough to be considered a transmission line, and you've got multiple receivers, termination is required, and AC termination is a great way to get the job done.
The PCB footprint cost is low -- it's one resistor, one capacitor. The placement for it is after the last receiver in the chain (NOT before it). I would add it, as if you find you have reflection issues or other signal integrity problems, it's tricky to add it after the board is fabricated.
If your clock is idle high, it'll just charge up the capacitor, and I imagine the first clock edge will suffer as the driver has to sink the current from the capacitor. If you can get dummy clocks out (while holding CS# de-asserted, for example), I think it would not be a problem.
Howard Johnson's High-Speed Digital Design covers this in detail as well.