I want to ask if it's a good practice to add or leave room for an AC termination with a driven clock signal like SPI CLK. With a driven clock signals I mean something like a clock that it isn't always active.
Since a driven clock can be assumed as a signal data line, if answer is affermative, should AC termination added to data lines to improve reliability?
It is only really useful with continuous clocks and even then is as much about dealing with different bias between say PECL and LVDS as anything else.
You would only use it in a data line if the data was DC restored in some way or coded with something like biphase or 8B10 that has a constant average value.
If one of the datasheets says AC couple, or if you cannot make the biasing work any other way (And DC conditions are not data dependent) then maybe, otherwise don't bother.
Regards, Dan.
Clocks are perfect for AC termination, because they are DC-balanced / and (hopefully) always at a 50% duty cycle. If yours (assuming a CMOS clock) is long enough to be considered a transmission line, and you've got multiple receivers, termination is required, and AC termination is a great way to get the job done.
The PCB footprint cost is low -- it's one resistor, one capacitor. The placement for it is after the last receiver in the chain (NOT before it). I would add it, as if you find you have reflection issues or other signal integrity problems, it's tricky to add it after the board is fabricated.
If your clock is idle high, it'll just charge up the capacitor, and I imagine the first clock edge will suffer as the driver has to sink the current from the capacitor. If you can get dummy clocks out (while holding CS# de-asserted, for example), I think it would not be a problem.
Howard Johnson's High-Speed Digital Design covers this in detail as well.
