How to implement a function using just NAND or NOR logic gates

I am trying to understand the process of creating combinatorial circuits. I understand that first we document the inputs and outputs, then create minterms and max terms, then push them into a k-map and get a function as an output. This function can then be implemented using logic gates.

The problem I have is, I don't understand the logic behind converting the equation that we got, such that I can implement the same circuit using just NAND or nor logic gates.

The image is from my book for converting a half adder circuit. I understand the steps taken but don't understand the reason why they took them. Thanks for the help.

• There are plenty of links to similar questions with good answers on the right side of this page. More can be found by searching. Nov 4, 2016 at 16:18
• Which bit don't you get? Nov 4, 2016 at 16:19
• Google De Morgan's Laws Nov 4, 2016 at 16:24
• I want to know the title of the book from which the photo were taken. Feb 7, 2021 at 17:22

Y = ABC+DEF+GHI+JKL...

Repeatedly apply de'Morgan's Theorem to convert all AND and OR and NOT operations into either NAND or NOR as required.

AND(A,B,C,D...) = NAND(NOT(A),NOT(B),NOT(C),NOT(D)...)

OR(A,B,C,D...) = NOR(NOT(A),NOT(B),NOT(C),NOT(D)...)

NOT(A) = NOR(A,0)

NOT(A) = NOR(A,A)

NOT(A) = NAND(A,1)

NOT(A) = NAND(A,A)

Although the other answers do explain the process to use deMorgan's to convert to NAND/NOR, they don't really answer the question if you look at the graphic of a half adder.

$$S = A \overline B + \overline A B$$ $$C = A B$$

deMorgan's, you get:

$$S = \overline {\overline {A \overline B} \cdot \overline {\overline A B}}$$ $$C = \overline {\overline{A B}}$$

The half adder constitutes 7 NAND gates because each of the AB terms is unique.

$$S = A \overline B + \overline A B$$ $$S = A \overline B + 0 + \overline A B + 0$$ $$S = A \overline B + A \overline A + \overline A B + B \overline B$$ $$S = A (\overline A + \overline B) + B (\overline A + \overline B)$$ $$S = A (\overline {A B}) + B (\overline {A B})$$ $$S = \overline {\overline {A (\overline {A B})} \cdot \overline {B (\overline {A B})}}$$ $$C = \overline {\overline{A B}}$$ The AB term is reused and now the half adder is 5 gates.

simulate this circuit – Schematic created using CircuitLab

• I don't understand why you are excluding NOT from the "fundamental" operations... Nov 4, 2016 at 16:28