As far as I am aware, in a FIFO as we keep reading it will eventually become empty i.e no more data inside and its output shall become 0x0. If we keep reading it after it has become empty, we shall cause an "underflow".
I am new to using Altera (Clock Crossing) FIFOs and what I have noticed in simulation is that the FIFO does NOT get completely empty i.e the last data word written to it stays at the output q even after empty is asserted by the FIFO itself and even if more rdreq is sent to this empty FIFO, the output simply does not become 0 which in my understanding would mean no more data inside.
In the megawizard, I did not find any option that controls this aspect of the FIFO behaviour. I have not yet done hardware simulation using signal tap II on a real FPGA to see what happens in it. What am I missing/misunderstanding here?