As far as I am aware, in a FIFO as we keep reading it will eventually become empty i.e no more data inside and its output shall become 0x0. If we keep reading it after it has become empty, we shall cause an "underflow".

I am new to using Altera (Clock Crossing) FIFOs and what I have noticed in simulation is that the FIFO does NOT get completely empty i.e the last data word written to it stays at the output q even after empty is asserted by the FIFO itself and even if more rdreq is sent to this empty FIFO, the output simply does not become 0 which in my understanding would mean no more data inside.

Here is result of simulation I did with the FIFO on its own: enter image description here

In the megawizard, I did not find any option that controls this aspect of the FIFO behaviour. I have not yet done hardware simulation using signal tap II on a real FPGA to see what happens in it. What am I missing/misunderstanding here?

  • \$\begingroup\$ Does the documentation say that in an underflow condition, the output will read as 0? Or that it will read as the last value from the queue? Or does it say the output is not defined? \$\endgroup\$
    – The Photon
    Commented Nov 5, 2016 at 1:20
  • 1
    \$\begingroup\$ There's no reason for the outputs to change from the last value read out. The "empty" flag tells you that the data is not to be used. \$\endgroup\$
    – Dave Tweed
    Commented Nov 5, 2016 at 2:00

1 Answer 1


I've designed a few FIFOs and the truth is that there is no reason for the FIFO to output zero when empty. Think of a FIFO as having two pointers: a write, and a read pointer. When you push data it is written to the write pointer address, and the write pointer is incremented. When you pop the FIFO the read pointer increments. The output of the FIFO is the data pointed by the read pointer. fifo

Now, if there is no data to pop, you simply do not increment the read pointer. So the output will have some data that is not valid, probably the last valid data. That is why you usually use empty and full signals.

Of course you can change this behavior, but usually it is not required. If the output data is not valid, you do not care about it.

  • \$\begingroup\$ OK, I will keep that in mind and this will require me to change my design. However, what is supposed to happen if/when we for whatever reason pop a FIFO that is already empty? \$\endgroup\$
    – quantum231
    Commented Nov 5, 2016 at 23:52
  • \$\begingroup\$ Doesn't matter, they are all X's for all you care. You should have an FSM that waits in its current state until the empty signal becomes non-active. So you stop, if the FIFO is empty. You should not pop an empty FIFO. This means there is an error somewhere. \$\endgroup\$
    – user110971
    Commented Nov 5, 2016 at 23:54

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