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I am just wondering that for Master SPI-CLK line is Output line while for Slave device it's input, is it logical or necessary to put the pull-up resistor on the SPI CLK line. What happens if we don't put pull up ? I am using 8-bit Microcontroller of PIC series and using spi interface for communication.

I am sorry for such basic question but i need to clear my doubt. Thanks

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    \$\begingroup\$ CMOS output drives both high and low. The pull up is irrelevant. \$\endgroup\$ – Tom Carpenter Nov 5 '16 at 11:22
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    \$\begingroup\$ @Tom Carpenter: correct but in most microcontrollers outputs can be configured also as open drain outputs... . So the need for a pull-up resistor depends on the configuration. \$\endgroup\$ – Curd Nov 5 '16 at 12:00
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It depends on how the SPI CLK output of the SPI master is configured by the firmware:

If it is configured as open drain output a pull-up resistor is needed.
If it is configured as push-pull output no pull-up resistor is needed.

I don't know the PIC Microcontrollers but I assume its outputs can be configured as open drain output. In that case a pull-up resistor is needed.

It'd be better, however, to configure it as push-pull output, because that results in shorter rise times for the CLK signal and saves power while the signal is in Low state.

Normally it should be possible to configure it as push-pull, because there is only one master that drives the SPI CLK signal (Open drain is only needed if there are more than one (possible) devices that drive the same signal line; the resulting signal then is a "wired-AND" of all output signals connected to the line).

So you are right: it shouldn't be necessary to have a pull-up resistor at the SPI CLK line, provided the output is configured as push-pull.

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As long as the Chip Select pin of your slave device is high it doesn't care what goes on with the clock or data lines.

It makes no sense to add a pull-up to the clock since the only time the slave cares about what happens on that line is when you are actively doing an SPI transaction.

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  • \$\begingroup\$ Except that, if the SPI clock is floating, the logic level sensed at the slave may toggle constantly. And, whatever the state of CS, most likely the input stage of CLK within the slave chip is kept powered on. So this may have unwanted side effects, like excessive power consumption, even if it doesn't affect the chip functionality. \$\endgroup\$ – dim Nov 5 '16 at 21:42
  • \$\begingroup\$ So... don't have it floating then. If you're that concerned about power consumption you won't be floating your pins anyway. \$\endgroup\$ – Majenko Nov 5 '16 at 21:43

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