Level-Shifter, a resistor i dont understand

I got a lot of help in understanding this circuit in a previous post.

I just don't understand the choice of R3 or why it is even there exactly.

EDIT: I just read my question and realized I give no context at all. This is supposed to be a levelshifter from 3.3V to 5V the Output requires near 5V for High and near 0V for Low.

Why is R3 1koHm? Is it to limit the current to the output although I though a digital input has negligible current draw? Or is it just cause I need something to create a voltage drop and i don't care about the current anymore? Or is 5mA just a standard for digital signals?

simulate this circuit – Schematic created using CircuitLab

Thank you guys alot

• Think about what would happen when Q2 is open and R3 isn't there. Nov 5, 2016 at 18:29
• @akaltar Nothing at all? I don't have any "consuming" device at all in the circuit. That would be a short circuit? But why not just use a 4.7kOhm resistor aswell? Nov 5, 2016 at 18:32
• R3 is a "pull up" resistor. If it's not there, the output will not go high (5V) when Q is off. Indeed you could use a 4.7 k ohm resistor as well. It depends on how quickly you want the output to go high when Q2 switches off. There will always be some capacitance on the output node and this cap will charge more quickly when R3 has a smaller value. Nov 5, 2016 at 18:47
• @FakeMoustache Ty alot. I wasn't aware this is a pull up resistor. After some reading up that actually makes sense now :D Nov 5, 2016 at 18:56
• As simply as possible, the transistor makes it go low and the resistor makes it go high. Next level of complexity- the resistor is higher resistance than the transistor 'resistance', so it will go high slower than it goes low. Nov 5, 2016 at 19:50

It's not a critical choice. If you were driving many TTL loads with Iih of 60uA each 1K would still be overkill for the DC level. There is one more consideration. The capacitance of the input must be considered. The Rc choice with this capacitance will determine the rise time.

What is more important here is why use two transistors to do this. If you put the input to the base of the second transistor you would only need a beta to 10 to saturate the transistor. If you use a more reasonable 10k pull-up there is not doubt at all. The inversion of the bit in the micro is much less expensive than the second transistor. Engineers must always be concerned with the cost of a product.

• Ty for helping me out :D Nov 5, 2016 at 18:57

Rise time and fall time are dependent on the source R * C load. OIbviously Low out is much lower than pullup R on collector. Which is a disadvantage for high speed circuits but Ok for simple low frequency switching circuits.

Vce in "switched mode" it only needs to drive the load capacitance with a reasonably low Rc and may range from 10M to <1K depending on path length power loss and speed requirements to control skew, latency and other delays.

Rb is >=10* Rc, thus R1 can be 100 * R3

This is due to reduction of hFE to <10% of max linear gain during saturation but 10:1 are guaranteed datasheet specs for Vce(sat)

Although every logic family is different, they share a similar push-pull style on the output stage , with bipolar for TTL and then FETs for CMOS.

This is an Advanced Schottky 74AS04 TTL logic "Inverter" and very similar in many ways to all TTL ( now ancient compared to CMOS.)

Open Collector may be similar to yours without the R3.