I am using two evaluation boards in my circuit. Counting the one I'm designing, there are three. I know the impedance of tracks on Board #1 and have control over the impedance of tracks on Board #2. The input impedance of the tracks on Board #3 is unknown. There is no termination at the end of the lines on Board #3.

At the interface between Board #2 and Board #3, I need to control the impedance. To that end, I will be source matching at the driver on Board #2, but what is the best way to deal with boundary?

Would it be best to have a termination at the end of the line on Board #2? Perhaps a shunt or AC Termination? This assumes my driver can support the power drain of the shunt.

Perhaps I should use a quarter wave transform? Ending the transform right at the input header to Board #3 might be effective?

The simplest solution might be to place the connector physically close to the driver so they are lumped. If I then add source termination resistors to the driver to match it to the impedance of Board #3, would the two boards communicate smoothly?

Since I don't know the impedance of Board #3, would it be reasonable to accurately measure the track's width and its distance from the ground plane and roughly calculate it?

Speed The edge rate of the data is ~750Mhz - 1GHz. I'm working with a rise time of about 1ns. I have space for a larger capacitive load if recommended. The output drivers of choice are the 74VCX245, but am open to changing them.

Board Layout Board #2 will have a solid ground plane between the output drivers and the connection to Board #3.

Connector Board #2 and Board #3 will connect via a 2x20 rectangular header. I am open to other suggestions.

Board #3 Board #3 is Texas Insrument's DAC7741 EVM. If you look at the data sheet, you'll see that there is not much information on the track design. The most I was able to extract was that the minimum track width is 10 mils, it is 1oz copper plated, and the layer (dielectric) thickness is approximately 0.014"

Physical Configuration The connection method I had in mind looks like this: enter image description here


  • \$\begingroup\$ What equipment do you have? Can you measure the impedance of board 3? Say, by making a test board with some BNC connected then: Board 3 -> test board -> network analyzer. Keep the test board as close to your board as possible to obtain accurate results. \$\endgroup\$
    – user110971
    Nov 5, 2016 at 23:32
  • \$\begingroup\$ Unfortunately I do not have a NA available to me. However, I do have a high-speed scope that might be useful. Generally, I have equipment found in a physics lab, including a fancy scope, but not sophisticated electronic equipment. \$\endgroup\$
    – Edgar P
    Nov 5, 2016 at 23:37
  • \$\begingroup\$ What do you mean "at the end of line"? Are the boards just cut off and brought together end-to end? Or on top of each other? How do you plan to provide ground continuity? It would be helpful to give a picture or drawings of how your boards are interfacing each other. \$\endgroup\$ Nov 6, 2016 at 0:17
  • \$\begingroup\$ Focusing on the interface: the boards will be on top of one another. The top board (Board #3) will connect to the bottom board via a 2x20 header. One row of the header connects the signal traces. The second row connects the grounds. I'm working on the PCB design and will upload it as soon as its available. \$\endgroup\$
    – Edgar P
    Nov 6, 2016 at 0:19
  • \$\begingroup\$ What is the frequency/edge rate of the signals? Again, how the ground is laid out on both boards, how it is exposed at the interface area? If you have eval boards, can you disclose them and give a link? Also, boards do not have impedance, particular traces do. \$\endgroup\$ Nov 6, 2016 at 0:26

1 Answer 1


With clarifications added, here is my answer. The particular device of interest is a 16-bit DAC. It has a PARALLEL interface, and settling time is 5us. This means that the converter should not be used with data changes faster than 5us (200 kHz sampling). This means that all concerns about edge rate and impedance matching have little to no grounds. The parallel interface with separate strobe and data has enough room at 5us rate to avoid any ringing that might emerge due to trace impedance mismatches. That's why the TI evaluation board does not have any special precautions for data input connector, and uses the cheapest 0.100" IDC headers. The 0.100 connectors have typical impedance of 100-120 Ohms, and the 10mil trace over 14mil substrate comes up to 78 Ohms.

Now, to get nice edges out of this setup, it is advisable to have the same kind of traces on the baseboard, and, since the drivers are thought of fast LVC245 nanosecond-grade buffers, a set of in-series resistors of about 47 Ohms would be in order, on driver side. They can be later adjusted for the best waveform. But again, you can do nothing, and the DAC interface will work just fine.

  • \$\begingroup\$ Thanks for the information. Could you share how you got the 47R value? 5us is the settling time for a Full Step Response of 20V. My signal is closer to 2V so I can switch the data much more quickly. It turns out that I can switch my data at 100 MHz or slightly over that. Settling time and sample rate are different in that regard. \$\endgroup\$
    – Edgar P
    Nov 6, 2016 at 3:57
  • \$\begingroup\$ 100 MHz is 10ns. Even if your total trace length is 4-6 inches, all reflections will die in under 2ns, so you still have a huge 8ns slack. The 47 Ohms is a ballpark starting number, to to bring the 20-Ohm driver close to a 80-Ohm trace. \$\endgroup\$ Nov 6, 2016 at 4:13
  • 2
    \$\begingroup\$ @EdgarP, minimum CS low timing is specified as 30 ns. This does not allow updating the DAC at faster than 33 MSa/s, and actually less because there's a required delay between strobing LDAC and the next time CS goes low. \$\endgroup\$
    – The Photon
    Nov 6, 2016 at 4:15
  • 2
    \$\begingroup\$ Looking at the timing diagram on page 6 of the datasheet, the update rate seems to be limited by the combination of \$t_{LS}\$ and \$t_{LH}\$, giving a maximum update rate of 25 MSa/s. \$\endgroup\$
    – The Photon
    Nov 6, 2016 at 4:16
  • \$\begingroup\$ Darn it, I think you're right. If I keep CS Low, then I believe I would be limited by the t_LX and t_LWD to 12.5 MHz. I really hope not! \$\endgroup\$
    – Edgar P
    Nov 6, 2016 at 5:09

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