# Impedance matching at the boundary between two PCB's

I am using two evaluation boards in my circuit. Counting the one I'm designing, there are three. I know the impedance of tracks on Board #1 and have control over the impedance of tracks on Board #2. The input impedance of the tracks on Board #3 is unknown. There is no termination at the end of the lines on Board #3.

At the interface between Board #2 and Board #3, I need to control the impedance. To that end, I will be source matching at the driver on Board #2, but what is the best way to deal with boundary?

Would it be best to have a termination at the end of the line on Board #2? Perhaps a shunt or AC Termination? This assumes my driver can support the power drain of the shunt.

Perhaps I should use a quarter wave transform? Ending the transform right at the input header to Board #3 might be effective?

The simplest solution might be to place the connector physically close to the driver so they are lumped. If I then add source termination resistors to the driver to match it to the impedance of Board #3, would the two boards communicate smoothly?

Since I don't know the impedance of Board #3, would it be reasonable to accurately measure the track's width and its distance from the ground plane and roughly calculate it?

Specifics:
Speed The edge rate of the data is ~750Mhz - 1GHz. I'm working with a rise time of about 1ns. I have space for a larger capacitive load if recommended. The output drivers of choice are the 74VCX245, but am open to changing them.

Board Layout Board #2 will have a solid ground plane between the output drivers and the connection to Board #3.

Connector Board #2 and Board #3 will connect via a 2x20 rectangular header. I am open to other suggestions.

Board #3 Board #3 is Texas Insrument's DAC7741 EVM. If you look at the data sheet, you'll see that there is not much information on the track design. The most I was able to extract was that the minimum track width is 10 mils, it is 1oz copper plated, and the layer (dielectric) thickness is approximately 0.014"

Physical Configuration The connection method I had in mind looks like this:

Thanks.

• What equipment do you have? Can you measure the impedance of board 3? Say, by making a test board with some BNC connected then: Board 3 -> test board -> network analyzer. Keep the test board as close to your board as possible to obtain accurate results. – user110971 Nov 5 '16 at 23:32
• Unfortunately I do not have a NA available to me. However, I do have a high-speed scope that might be useful. Generally, I have equipment found in a physics lab, including a fancy scope, but not sophisticated electronic equipment. – Edgar P Nov 5 '16 at 23:37
• What do you mean "at the end of line"? Are the boards just cut off and brought together end-to end? Or on top of each other? How do you plan to provide ground continuity? It would be helpful to give a picture or drawings of how your boards are interfacing each other. – Ale..chenski Nov 6 '16 at 0:17
• Focusing on the interface: the boards will be on top of one another. The top board (Board #3) will connect to the bottom board via a 2x20 header. One row of the header connects the signal traces. The second row connects the grounds. I'm working on the PCB design and will upload it as soon as its available. – Edgar P Nov 6 '16 at 0:19
• What is the frequency/edge rate of the signals? Again, how the ground is laid out on both boards, how it is exposed at the interface area? If you have eval boards, can you disclose them and give a link? Also, boards do not have impedance, particular traces do. – Ale..chenski Nov 6 '16 at 0:26

• Looking at the timing diagram on page 6 of the datasheet, the update rate seems to be limited by the combination of $t_{LS}$ and $t_{LH}$, giving a maximum update rate of 25 MSa/s. – The Photon Nov 6 '16 at 4:16