# Clock Implementation Design Warning on Spartan 3E

I am working with a SPARTAN 3E-FT256 on Xilinx 14.1, and have to generate a 25 MHz clock from the onboard 50MHz clock.I am accomplishing this with a Digital Clock Manager.

These are my UCF designations :

NET "CLK_50MHZ" LOC = "C8" | IOSTANDARD = LVCMOS33 ;   //GCLK 10
NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%;              //DCM_X0Y1


DCM Instantiation :

wire clk_ibufg;
wire clock;
wire CLK0_OUT;

IBUFG clk_ibufg_inst ( .I(CLK_50MHZ) , .O(clk_ibufg) );
BUFG  clk_bufg_inst  ( .I(clock) , .O(clk));

ClockManager1 clock_converter (
.CLKIN_IN(clk_ibufg),
.CLKFX_OUT(clock),
.CLK0_OUT(CLK0_OUT)
);


I am very uncertain about the use of IBUFG and BUFG, but the datasheet seems to prefer the connections ---IBUFG to DCM to BUFG---- for minimum skew.

The warning I get :

"The following Clock signals are not routed on the dedicated global clock routing resources. This will usually result in longer delays and higher skew for the clock load pins. This could be the result of incorrect clock placement, more than 8 clocks feeding logic in a single quadrant of the device, or incorrect logic partitioning into the quadrant(s). Check the timing report to verify the delay and skew for this net Net Name: clock"

Is there any way to specify which BUFG or IBUFG to use? Why am I getting this warning?

• I presume you generated ClockManager1 using the CoreGenerator tool? If not, how did you make it? If so, what settings did you choose for the output buffers of the DCM? – Tom Carpenter Nov 6 '16 at 14:36
• You presumed correctly.I was using those automatic buffers option when generating the DCM. Removed IBUFG and BUFG and it works without a warning. However, I do get one during synthesis that says "Signal <CLK0_OUT> is assigned but never used". From the datasheet, this signal is to be used to employ feedback for deskewing. How do I feed it back into the DCM and get rid of this warning? Because on the IP Core generation template it shows CLK0_OUT being automatically fed into CLK_FB. – Ahmed Ali Abbasi Nov 6 '16 at 14:46
• It may well be done internally, in which case you can just ignore that output - in the instantiation, just put .CLK0_OUT() and it should remove the warning. – Tom Carpenter Nov 6 '16 at 14:50
• In terms of feedback, one of the documents (pg10) specifies that in the feedback options you can have: "No feedback. Allowed if using only the CLKFX or CLKFX180 outputs." Given you are using only the CLKFX port, no feedback is fine. – Tom Carpenter Nov 6 '16 at 14:53

Because you are using the CoreGenerator wizard, most of the low level stuff can be selected as part of the wizard meaning you don't need to instantiate them manually.

For the outputs, as you have selected auto, you don't need to add a BUFG. Otherwise the DCM will probably instantiate a BUFG for the output which then has to feed your BUFG (i.e. two in a row). Two global clock buffers shouldn't be placed in a row, firstly because there is no need to, and secondly because it means the signal has to leave the global clock network it is on from the first BUFG to get to the input of the second BUFG, hence your warning.

You should also be able to select that an IBUFG be used in the DCM wizard for the input, which means again, you need not instantiate it manually.

From the comments you also mention a warning about CLK0_OUT being unused. You have connected this output to a wire, and I can only assume that you are not then connecting it anywhere. CLK0 is used for feedback as you say, but according to the Xilinx App Note XAPP462 (pg10) you don't need feedback if using only the CLKFX output port, which in your case is true.

"No feedback. Allowed if using only the CLKFX or CLKFX180 outputs."

• So, I need not instantiate an IBUFG or a BUFG for a DCM.However, the only option regarding buffers is the one that asks whether or not to use clock buffers for outputs. – Ahmed Ali Abbasi Nov 6 '16 at 16:16
• @newbie couldn't remember if there was an input option. But it will most likely infer an IBUFg even if you don't add it because that is the only way to get the clock from an input pin to the DCM. – Tom Carpenter Nov 6 '16 at 16:48
• One further query, on top of everything else, Which IO pin do I use for a synchronous active high reset? From the data sheet, all I get is that "BTN_SOUTH is also used as a soft reset in some FPGA applications." I find no other documentation on even what a soft reset is. – Ahmed Ali Abbasi Nov 7 '16 at 19:54