I need to detect a short pulse (~ 100nS) with the comparator. So I hope that the short zero-crossing pulse will trigger the comparator interrupt, but I wasn't able to find any information upon reaction time/comparator speed of my controller.

Moreover, I'd like to keep CPU clock speed low (1 MHz). Hope that the clock speed is not related to the comparator.

I concerned more about minimum pulse length than reaction time.

  • 1
    \$\begingroup\$ Design a pulse stretcher/conditioner for it. \$\endgroup\$
    – jonk
    Nov 6, 2016 at 20:15
  • \$\begingroup\$ @jonk I'd like to keep the schematic as simple as possible. So if no stretcher needed I will gladly skip one. \$\endgroup\$ Nov 7, 2016 at 7:53
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    \$\begingroup\$ I think you already know that it cannot be guaranteed, given the datasheet info. If you are bent on avoiding external circuitry and willing to experiment and see, then that's not hard to do. The answer you have already is fairly convincing that you will have problems, though. A stretcher isn't hard (there are ICs for this -- 74121 for example, or even smaller, the LTC6993.) Discrete isn't even hard (and lots cheaper if you only count part costs.) I tried and I can't find a guarantee for you on this CPU. So validate through thorough testing over part variations, or do something else, I think. \$\endgroup\$
    – jonk
    Nov 7, 2016 at 8:02

1 Answer 1


The datasheet link you provided was for the shorter summary datasheet. You need to look at the complete datasheet to get the comparator propagation delay.


On page 384 the analog comparator propagation delay (the time delay between a change in the comparator input to a change in output) is listed as 500ns typical at VCC=4.0V or greater. Also page 309 says that "The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles".

If the CPU wants to use the comparator result an interrupt is not guaranteed to trigger any sooner than 2 clock cycles + 500ns + plus the interrupt latency from the CPU core itself.

When the datasheet says the comparator is synchronized on the clock they mean that the comparator is sampled by a clocked flip flop. Therefore any pulse output by the comparator that is less than 1 clock cycles cannot be guaranteed to be latched. At 1MHz the minimum allowed pulse would thus be 1us.

  • \$\begingroup\$ Could you please add more information about "propagation delay" term? Is it the shortest pulse to be detected? Or it is the time from the beginning of the pulse (let's say the signal slope) to the time some event inside the CPU will go into live? \$\endgroup\$ Nov 6, 2016 at 19:30
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    \$\begingroup\$ @RomanMatveev It's the latter, and hence not relevant to your problem. \$\endgroup\$
    – JimmyB
    Nov 7, 2016 at 9:13

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