The datasheet link you provided was for the shorter summary datasheet. You need to look at the complete datasheet to get the comparator propagation delay.
On page 384 the analog comparator propagation delay (the time delay between a change in the comparator input to a change in output) is listed as 500ns typical at VCC=4.0V or greater. Also page 309 says that "The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles".
If the CPU wants to use the comparator result an interrupt is not guaranteed to trigger any sooner than 2 clock cycles + 500ns + plus the interrupt latency from the CPU core itself.
When the datasheet says the comparator is synchronized on the clock they mean that the comparator is sampled by a clocked flip flop. Therefore any pulse output by the comparator that is less than 1 clock cycles cannot be guaranteed to be latched. At 1MHz the minimum allowed pulse would thus be 1us.