Firstly, Gigabit links are generally much closer to sine waves than the more square low-speed signals, so you can treat them as such in a first approximation (you won't be far off).
Frequency wise, you have to be a little careful. Every transition in a Gigabit link translates to the next piece of data, so a full 1-0-1 cycle would represent a full 'clock' cycle.
The net result of this is the effective operating frequency of the link is half the line rate (i.e. 1.5GHz for a 3Gb/s link). In other words, you get 2 bits of data for each 1-0-1 transition.
With respect to routing the traces, try to avoid more than 2 vias for each trace of the differential pair when getting from the source to the destination. At higher frequencies it's also worth sandwiching the traces between a pair of ground planes, and using blind or microvias - at 10Gb/s even a normal through-via can create problems. We normally use a 2-core construction with a blind via through the top half and sandwich the serial links between grounds on layers 2 & 4. You may also want to consider PCB materials other than FR4, depending on the trace distance, especially when going > 5 Gb/s. For lower speeds and short routes this is probably overkill, but you should always have a continuous reference plane next to the traces in any case.
If you're really worried, do a proper signal integrity model using something like HyperLynx or a 3D waveform solver, but you probably don't need to worry about that unless (like us) you have > 144 x 10 Gb/s links in a dense board.
Just to summarise some rules of thumb:
- Keep traces short (< 10 inches or shorter, depending on frequency).
- Antipads on unconnected layers around vias (reduces excess capacitance).
- Minimise via transitions.
- Keep reference plane continuous.
- Microstrip or stripline.
- Match skew on differential traces before your vias.
- Space from other traces by at least 5x width of traces in differential pair (preferably more).