# debounce state machine graph

I need to make the graph for a state machine that debounces an input signal, maintaining the current up/low input signal for a certain time, and to calculate this time im using a counter. I am having a loooot of trouble with designing the graph for this state machine so any help at all would be welcome. I am very inexperienced with hardware so please just warn me if you need more details.

edit:I forgot to mention that I already possess the state machines of the circuit(sort of) I really only need help with making the graphs for it. this I will be adding pictures of the signals and circuit.

edit2:following the step by step suggestion I have made an attempt to make the diagram, I would like to know if I was able to reach the proper answer.

please note:the variables on the arrows are: the entry signal,time out and the outputs inside the bubbles are: output,clear

• Why do you think you need a graph just to write some debouncing code? This is a well solved and rather trivial problem. Nov 7, 2016 at 12:06
• For my project , our teacher has instructed that when we implement state machines , we need to make all of the steps provided by him, regardless if actually needed or not, and im having a lot of trouble, and wasnt successful in my research Nov 7, 2016 at 12:11
• I refer you to the best resource I have found Jack Ganssle ganssle.com/debouncing.pdf and ganssle.com/debouncing-pt2.htm Nov 7, 2016 at 12:41
• @OlinLathrop: The question is not really about how to debounce a signal; that's just the context for the actual question, which is about how to measure a specific time span using a given clock and a state machine. Nov 7, 2016 at 13:03
• Note that the time interval shown in the diagram does not match the description: "Only declare an input change after signal has been stable for at least 5ms". The interval matching that description would start after the last glitch, not at the beginning of the first one. Nov 7, 2016 at 13:06

I'm not going to do your homework assignment for you, but simply give you a few clues to get you started.

First define the states. These are "situations" in which the hardware or logic device can achieve. I would suggest the following four states:

State A - OFF - the switch input is debounced and is definitely stable in the OFF condition and the circuit output is in the OFF ( call it "0", or logic LOW) condition.

State B - OFF with ON Detected - Output is LOW, but an instantaneous high has been detected on the switch input (e.g. someone is beginning to push the switch and it is bouncing).

State C - ON - the switch input is debounced and is definitely stable in the ON condition and the circuit output is in the ON ( call it "1", or logic HIGH ) condition.

State D - ON with OFF Detected - Output is HIGH, but an instantaneous LOW has been detected on the switch input (e.g. someone is beginning to release the switch and it is bouncing).

Next, you have to define the Transition Conditions that lead you from one state to the next. These are the arrows between the bubbles in a traditional state diagram. For example, to get from State A to State B you need a Transition Condition called something line "Push Detected" or "On Detected". To get from State B to A you need a condition called "Release Detected" or similar.

You will also need a Parametric Variable. In this case that would be a Timer or a Clock Counter. A variable that increments by a fixed value, like 1 milli-second. While the state remains in State B If the timer gets to 5 milli-secs, you have a Transition Condition called something like "Time Out" which takes you to State C.

See? You have to "spell it out" in bubbles, arrows and variables just like you yourself are the logic circuit that is performing the debouncing task. Even a simple task like debouncing a switch can have a pretty complicated state machine diagram. The code to actually do the debouncing in a real application will be simpler to write than drawing the state machine diagram. But drawing the state machine and thinking the problem through is an excellent way to learn the topic.

Try to use other State Machine Diagram examples (e.g. from text books or on-line resources) for other problems to guide your efforts with your present task.

• Hello, first of all Id like to say I am very thankful for your help, but would you be so kind as to give me feedback on my attempt?I have edited my question with my attempt. Nov 7, 2016 at 14:05
• Your diagram is a bit hard to follow because the names are so cryptic. Each state should have a concise name or at least a tag (e.g. A,B,C,etc. or 0,1,2,3, etc.) The cryptic abbreviations are OK if you provide a legend to describe them. Also, the state machine should normally "speak for itself". That is, without reference to a specific logic device hardware solution. Is it part of your homework assignment to also design the hardware circuit? Nov 7, 2016 at 15:14
• It is not, the assigment was just to create the diagram and from it, the truth table with the states and the fli flops, which I was able to successfully accomplish, again thank you very much for your help Nov 8, 2016 at 3:06

Since this is a homework question, I'll just give you some hints to get you started, rather than a complete answer.

The key concept for using a synchronous state machine to measure time intervals is based on the implicit assumption that the state machine spends a certain minimum time in each state, and that time is the period of the clock.

Therefore, to measure a specific time interval, you need to figure out how many clock periods it is going to be, and then have that many states in your state machine that it sequences through. The elapsed time from the first state to the last state will be the required time interval.

The most efficient way to encode a large number of states is to use a binary counter. Is this enough to get you going?

• Im sorry, I believe I was not clear enough about what is my actual problem, I have edited my question in order to do so.Again , I thank you very much for your time. Nov 7, 2016 at 13:25
• You don't needed that many states if you have access to a data path which includes, e.g. a counter and a comparator Nov 7, 2016 at 13:55
• @vicatcu: The state of the counter becomes part of the state of the overall machine, so yes, you really do have that many states. Nov 7, 2016 at 13:56