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I have created the following D Flip-Flop, which works as expected. I am now trying to implement an asynchronous reset to it. How can I edit my circuit so that when the button is pressed, Q is set to 0 and Q' is set to 1 immediately, regardless of whether the clock is on the positive or negative edge?

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Logism has a D Flip Flop with an asynchronous reset built in, but I would like to create my own.

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  • \$\begingroup\$ What you have is not a D flip-flop, since it is not edge triggered. To see this, keep the clock high and change the data - the outputs will change without a clock edge. \$\endgroup\$ – WhatRoughBeast Nov 7 '16 at 22:25
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The gate-level logic of of various logical functions (D-flops etc.) has been solved by industry 40 years ago. Please study reference databooks from manufacturers like this one, from Texas Instruments.

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  • \$\begingroup\$ imgur.com/a/KwlJy I don't know what I'm doing wrong but I can't get that circuit to work. I am far from making sense of it at all. For example, the bottom input wire to the very top NAND gate is also input to the third down NAND gate, and nothing else. Forgive my elementary understanding of digital circuits, but is this wire doing anything at all? It cannot receive voltage from anywhere? Nonetheless, my version of this circuit does not work at all. Initially, both Q and Q' are set to 1, set 'Preset' to 1 and then Q goes to 0, Q and Q' never change with respect to D or the clock signal. \$\endgroup\$ – KOB Nov 8 '16 at 0:25
  • \$\begingroup\$ I believe there there should be a connection of your blue wire to the output of second triple NAND gate. Also , Q and Q' cannot be both "1". \$\endgroup\$ – Ale..chenski Nov 8 '16 at 0:42
  • \$\begingroup\$ imgur.com/a/9FizK It's still a very similar situation. Initially, Q and Q' are 1, if Preset is 1 then Q goes to 0, Clock and D never change the output at Q or Q'. I understand that my initial circuit in my question is not an exact flip-flop as the output changes anytime the clock signal is high, rather than only being able to change only when the clock switches from high to low - but it works fine for what I am trying to do. Is there any solution to that circuit that allows reset to set Q to 0 and Q' to 1 regardless of what D and the clock signal are at any given time? \$\endgroup\$ – KOB Nov 8 '16 at 1:00
  • \$\begingroup\$ This is the circuit. You probably are using some inadequate circuit simulator if you can get both Q and Q' at 1. Or initial conditions are conflicting, Set and Reset should be set 1 initially. \$\endgroup\$ – Ale..chenski Nov 8 '16 at 1:29
  • \$\begingroup\$ Ahh, I had set as 1 and reset as 0 initially and thought that setting reset to 1 was supposed to perform the reset. Seems to be working as expected now, thank you! \$\endgroup\$ – KOB Nov 8 '16 at 1:37
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Asynchronous sets and resets are done by bypassing the clock portion of the flip flop and controlling the latch directly:

schematic

simulate this circuit – Schematic created using CircuitLab

The NAND gates and NOT gates in the enable portion of the schematic can be combined into just NAND gates, I added the NOT gates to keep my schematic similar to yours.

However, this is not really a clocked d -flip flop, the 'Clock' as in your schematics is actually an enable line. A rising edge clock can be implemented using an AND gate and a series of NOT gates, shown below:

schematic

simulate this circuit

This works because each of the NOT gates has a small amount of delay from input to output. The output of the AND gate becomes a short pulse that only happens on the rising edge of the clock signal. The Output net then connects to the clock signal as you have it, and thus the flip flop can only be changed when the clock signal rises.

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