Asynchronous sets and resets are done by bypassing the clock portion of the flip flop and controlling the latch directly:
simulate this circuit – Schematic created using CircuitLab
The NAND gates and NOT gates in the enable portion of the schematic can be combined into just NAND gates, I added the NOT gates to keep my schematic similar to yours.
However, this is not really a clocked d -flip flop, the 'Clock' as in your schematics is actually an enable line. A rising edge clock can be implemented using an AND gate and a series of NOT gates, shown below:
simulate this circuit
This works because each of the NOT gates has a small amount of delay from input to output. The output of the AND gate becomes a short pulse that only happens on the rising edge of the clock signal. The Output net then connects to the clock signal as you have it, and thus the flip flop can only be changed when the clock signal rises.