I am creating a homebrew computer and am stuck on how to design/approach handling data requests between two different sections. I am creating it from mostly 74HCxxx series logic chips.
I have a homebrew CPU that runs at 1Mhz and has a bus to the RAM. It has 32 address lines and 32 data lines along with a Clock and Read lines. So an address is placed on the address lines and if the Read line is high then it expects the appropriate data to be placed on the data lines immediately. If the Read is low then the CPU also places a value on the data lines and the memory should update at the next clock tick. All very simple and works because the SRAM is comparatively fast (~50ns) and easily meets the timing needs of the CPU (1000ns).
I have now created a separate piece of hardware which is a video driver. It works at 12.587Mhz in order to output a low res VGA signal. It internally has some SRAM memory that stores the data for display. This works fine on its own.
But I have no idea of the correct approach to getting the CPU to be able to send data to the video driver. I want the video driver to be memory mapped and so when the CPU writes to a defined range of memory addresses the video driver will notice this and pick up the new value and store it internally. It would be nice to be able to also read from the video driver memory but that is optional.
I am a programmer and have no training in electrical enginerring so this might be trivial to others but not obvious to me. Should I be looking at FIFO buffers? Do I need some complicated interface between the two? My concern is that they are going at different clock speeds and so sometimes they will clash in timing?