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Why do I only get 00? I should be getting a counter on the positive edge of the clock. How do I correct it?

The 8-Bit Synchronous Counter using T Flip-Flops and AND Gates Consider the circuit in Figure 1. It is a 4-bit synchronous counter which utilizes four T-type flipflops.
The counter increases its value on each positive edge of the Clock signal if the Enable signal is high, since it is an active-high signal. The counter is immediately cleared to 0 by setting the asynchronous Clear signal low, since it is an active-low signal. The output of the leftmost flip-flop in the diagram is considered to represent the LSB of the counter. enter image description here

module lab4part1(SW, KEY, HEX1, HEX0);
    input [1:0] SW;
    input  [0:0] KEY;
    output [0:6] HEX1,HEX0;

    wire [6:0] W;
    wire [7:0] S;

    assign W[0] = SW[1] & S[7];
    assign W[1] =  W[0] & S[6];
    assign W[2] =  W[1] & S[5];
    assign W[3] =  W[2] & S[4];
    assign W[4] =  W[3] & S[3];
    assign W[5] =  W[4] & S[2];
    assign W[6] =  W[5] & S[1];


    tff0 u1 (SW[0],KEY[0],S[7]);
    tff0 u2 (W[0], KEY[0],S[6]);
    tff0 u3 (W[1], KEY[0],S[5]);
    tff0 u4 (W[2], KEY[0],S[4]);
    tff0 u5 (W[3], KEY[0],S[3]);
    tff0 u6 (W[4], KEY[0],S[2]);
    tff0 u7 (W[5], KEY[0],S[1]);
    tff0 u8 (W[6], KEY[0],S[0]);

    seg7 (S[3:0] , HEX0 );
    seg7 (S[7:4] , HEX1 );

endmodule 

module tff0(T, Clock, ClearN, Q);
    input T, Clock, ClearN;
    output reg   Q;

    always @ ( posedge Clock, negedge ClearN)
            if ( ~ClearN )begin 
                Q <=0;
            end
            else  if ( T ) begin
                Q <= !Q;
            end

endmodule

module seg7(bcd,leds);
 input [3:0] bcd;
 output reg [6:0] leds;

 always @ (bcd)
 case (bcd)
 0:  leds = 7'b0000001;
 1:  leds = 7'b1001111;
 2:  leds = 7'b0010010;
 3:  leds = 7'b0000110; 
 4:  leds = 7'b1001100;
 5:  leds = 7'b0100100;
 6:  leds = 7'b0100000;
 7:  leds = 7'b0001111;
 8:  leds = 7'b0000000;
 9:  leds = 7'b0000100;
 10: leds = 7'b0001000;
 11: leds = 7'b1100000;
 12: leds = 7'b0110001;
 13: leds = 7'b1000010;
 14: leds = 7'b0110000;
 15: leds = 7'b0111000;
 default: leds = 7'bx;
 endcase

 endmodule
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  • \$\begingroup\$ You forgot to ask a question. \$\endgroup\$ – toolic Nov 8 '16 at 1:53
  • \$\begingroup\$ @toolic Perhaps "how to correct it i only get 00, when i should be getting a counter on the positive edge of the clock" is the request. Of course, it's missing some punctuation and clarity. \$\endgroup\$ – ζ-- Nov 8 '16 at 2:12
  • 1
    \$\begingroup\$ Try to use consistent notation. No reason to declare as N:0 and 0:N in the same module. \$\endgroup\$ – jbord39 Nov 8 '16 at 2:34
  • \$\begingroup\$ Check your log file. I would be a supersized if there was not warnings on u1 through u8. \$\endgroup\$ – Greg Nov 8 '16 at 5:41
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You define module as tff0(T, Clock, ClearN, Q); but feeding it with tff0 u1 (SW[0],KEY[0],S[7]);, where SW[0] is used as T, KEY[0] is used as Clock, S[7] is used as ClearN, and output Q is unconnected.

Of course, as you messed wires for tff0, array S, as used only as an input, does not change, and is always a default value as it was at the start (0).

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