CD4048 datasheet confusion

Question

I was looking at the datasheet of CD4048, a multifunction gate IC when I was a bit disturbed by the output circuitry, controlled by Kd in figure 2.

When Kd is pulled to negative, the output is supposed to be high-impedance (floating), no matter the logic of the 8 inputs, but the way they've done it disturbs me.

This looks like a short circuit. Am I missing something? Am I interpreting the schematic wrong? Is this normal? I feel like the schematic would make more sense if both gates were non-inverting instead.

Answer 1

You have swapped NMOS for PMOS. In the original diagram, the upper FET is PMOS and the lower FET is NMOS. In your diagram with the simplified symbols, you have the upper FET as NMOS and the lower FET as PMOS.

In the more detailed symbol, the arrow represents the PN junction between the back-gate and the channel. I'm not sure the origin of the simplified symbols, but they seem to be based on a "tale for children and computer programmers", where they try to make the FET symbol more like the symbol for the BJT with similar behavior.

If Kd is low, then we know the NAND gate output is high, regardless of the other input. That means the PMOS is in a non-conducting state.

If Kd is low, then inverse of Kd is high. That means the NOR gate output is low, regardless of the other input. So the NMOS is also in a non-conducting state.