I am trying I2S input and I2S output on TI Device. Well, I want to know I2S SCK usage. Deivce constitution is below:
DAC(SLAVE) <--I2S-- TI-DEVICE(MASTER) <--I2S-- ADC(SLAVE) x4
I think that BCLK(Bit clock) and WCLK(Word clock) is transmit cycle(not sampling) of digital data. So there is possibility that each ADCs sampling cycle will be deviate(depend on crystal accuracy). But, sampling cycle will not be deviate with SCK. Sampling cycle will be depend MASTER's clock.
Do I understand correctly? Excuse me, I do not have knowledge of I2S...