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I am trying I2S input and I2S output on TI Device. Well, I want to know I2S SCK usage. Deivce constitution is below:

DAC(SLAVE) <--I2S-- TI-DEVICE(MASTER) <--I2S-- ADC(SLAVE) x4

I think that BCLK(Bit clock) and WCLK(Word clock) is transmit cycle(not sampling) of digital data. So there is possibility that each ADCs sampling cycle will be deviate(depend on crystal accuracy). But, sampling cycle will not be deviate with SCK. Sampling cycle will be depend MASTER's clock.

Do I understand correctly? Excuse me, I do not have knowledge of I2S...

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  • \$\begingroup\$ What chips are you using? \$\endgroup\$ – CL. Nov 8 '16 at 8:33
  • \$\begingroup\$ MASTER is CC1310 and SLAVE is PCM3168A(TBC). \$\endgroup\$ – EarleyJP Nov 8 '16 at 9:15
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The PCM1368A datasheet says in section 9.3.4:

The PCM3168A device requires an external system clock input applied at the SCKI input for ADC and DAC operation. The system clock operates at an integer multiple of the sampling frequency, or fS.

As long as the CC1310's I²S module generates BCLK and WCLK in sync with the master clock (which it does), there will be no deviation.

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