I am trying to generate some waveforms which are phase shifted from an input signal.
The input signal is around 4.4 MHz and is a square wave at 50% duty. I need a 0 degree and 90 degree phase shift of this waveform, and each wave must be 50% duty cycle. I may also need to shift both waves by 180 degrees i.e. 180 and 270 degrees. (This is for PAL video.)
My idea was to use a PLL to up the frequency to 17.6 MHz. Then, a decade counter and two OR gates would generate the 0 and 90 degree waves. An inverter resets the counter so it overflows at 4. An XOR chip would be needed for the 180 degree shift. The PLL would be a 4046-type device and would also need a divide by 4 counter.
I tested this in a circuit simulator:
Great... the concept works. However, I'm quite limited by board space, and cost. I would need five chips plus the PLL chip to do this. I have never programmed a CPLD before, but it sounds like the perfect application for one. Would I be able to do a basic task like this using a low end CPLD like this one? Or would 32 macrocells be insufficient? Is there a rough estimate for how many macrocells would be required per basic gate, and how many would be required for a complex device, such as a counter?