I am trying to generate some waveforms which are phase shifted from an input signal.

The input signal is around 4.4 MHz and is a square wave at 50% duty. I need a 0 degree and 90 degree phase shift of this waveform, and each wave must be 50% duty cycle. I may also need to shift both waves by 180 degrees i.e. 180 and 270 degrees. (This is for PAL video.)

My idea was to use a PLL to up the frequency to 17.6 MHz. Then, a decade counter and two OR gates would generate the 0 and 90 degree waves. An inverter resets the counter so it overflows at 4. An XOR chip would be needed for the 180 degree shift. The PLL would be a 4046-type device and would also need a divide by 4 counter.

I tested this in a circuit simulator:


Great... the concept works. However, I'm quite limited by board space, and cost. I would need five chips plus the PLL chip to do this. I have never programmed a CPLD before, but it sounds like the perfect application for one. Would I be able to do a basic task like this using a low end CPLD like this one? Or would 32 macrocells be insufficient? Is there a rough estimate for how many macrocells would be required per basic gate, and how many would be required for a complex device, such as a counter?


3 Answers 3


This only addresses the second part of your question, how to know what size of CPLD you need for a design:

Typically the amount of logic you can fit in a CPLD is limited by either the number of flip-flops (or other latches) or the number of I/O's in your design. Generally you get one flip-flop per macrocell, and something less than one I/O pin per macrocell. The basic design allows one I/O per macrocell, but often some of the I/O's on the die are not bonded out due to the limited number of pins in a given package.

So, for your design, you have 14 flip-flops for your two counters and you're good. Normally I wouldn't recommend using programmable logic for the phase comparator in your design but at 17.5 MHz and if you aren't very particular about how exactly you match up the input and output phase, you should be able to get away with it. You'll still need an external VCO and filter circuit. So with a 32-macrocell CPLD you should have no problem fitting the digital elements from this design with some room left over for other glue logic you might need.

That said, generally a design for such a small CPLD is so simple that you can code it up in an hour or so and use the vendor's design tool to be sure it fits before moving forward. All of the CPLD vendors I know of offer free versions of their design tools that cover almost all sizes of CPLD.

Finally, though the estimate of 1 flip-flop per macrocell is accurate for classical CPLDs like the one you linked to, some vendors (Altera & Lattice come to mind) have taken a major architectural excursion in their newest CPLD families. These devices are more like mini-FPGAs than like the classical CPLD, and I'm not sure that they calculate their "macrocell-equivalent" sizes according to this formula. The new devices are likely to have more flip-flops per device, but not allow very wide fan-ins to the logic in each cell.

As for the other part of your question, is this a good use for a CPLD, that's a tougher question. I don't see any reason not to use one, but maybe someone will come up with a clever way to build this circuit at lower cost / less board space / lower power, or whatever.

  • 1
    \$\begingroup\$ Some FPGAs, at least, have integrated PLLs. If he can find a CPLD with a built-in PLL, it will knock the part-count down to one device. \$\endgroup\$ Commented Feb 19, 2012 at 3:01
  • \$\begingroup\$ I looked at Altera's Max V, and its not obvious from a quick datasheet read if it has this capability. More likely he'd have to go to a minimal FPGA (Altera Cyclone III or so) to get an on-board PLL. Whether that's a good cost trade-off would need more research. \$\endgroup\$
    – The Photon
    Commented Feb 19, 2012 at 3:05
  • \$\begingroup\$ The MAX V spec sheet makes a mention of a "Digital PLL" (see here), but I could not find any other information on it. The Xilinx Cool-Runner 2 claims to have a "Clock-Doubler" that is "Selectable for each MacroCell" (see here), but I'm not familliar with xilinx parts. \$\endgroup\$ Commented Feb 19, 2012 at 3:15
  • \$\begingroup\$ Xilinx haven't released a new CPLD for close to 10 years -- I'm sure they won't have a PLL that can do what he wants (quadrupler). But Lattice or Altera may have it. \$\endgroup\$
    – The Photon
    Commented Feb 19, 2012 at 3:21
  • \$\begingroup\$ It looks like the Coolrunner-2 "clock doubler" just refers to the ability for each flip-flop to be configured for dual-edge (ddr-like) triggering. \$\endgroup\$
    – The Photon
    Commented Feb 19, 2012 at 3:24

I would suggest that a simpler approach might be to simply use a delay circuit, rather than a PLL. For example, feeding the signal through an RC circuit and a comparator whose input is set at half-rail can generate a phase delay from just over 0 to almost 90 degrees; using two resistors and two capacitors one can push the delay beyond 90 degrees. Tweak the resistor and cap and you should be able to get a delay pretty close to 90 degrees.

  • \$\begingroup\$ The problem is the input frequency may change - I thought about using a fixed RC network but I'm looking at working at either 3.5 MHz or 4.4 MHz. \$\endgroup\$
    – Thomas O
    Commented Feb 19, 2012 at 11:23
  • \$\begingroup\$ I don't know what level of precision and stability you're looking for, but a perfect square wave driving an RC circuit which feeds a comparator which checks against mid-rail will yield a delay which is inversely proportional to frequency. The larger the RC relative to frequency, the closer the lag will be to 90 degrees. The primary difficulty with the circuit is that increasing RC relative to frequency will reduce the amplitude of the signal feeding the comparator and make it more sensitive to half-rail. \$\endgroup\$
    – supercat
    Commented Feb 19, 2012 at 18:32
  • \$\begingroup\$ Of particular interest, btw, is the fact that the delay is not proportional to R and C. If one uses feedback to generate the half-rail (i.e. adjusts the "half-rail" voltage based on output duty cycle) it should be possible to construct a circuit which is relatively insensitive to component variations. One could push the delay to 90 degrees either by adding a second delay circuit which was adjusted for an "absolute" time (but only had to deal with the error between the pseudo-90-degree signal and a real one) or else by using an integrator instead of an RC network. \$\endgroup\$
    – supercat
    Commented Feb 19, 2012 at 18:35
  • 1
    \$\begingroup\$ If you do want to use a PLL, you could simplify your logic by using a pair of D flip flops with regular and inverting outputs, clocked by the output of a PLL running at 4x the input frequency. Wire the non-inverted output of the first to the second, and the inverted output from the second to the first. The four outputs (regular and inverted, from each flop) will each output a square wave that's 1/4 the PLL frequency, in each of four phases. \$\endgroup\$
    – supercat
    Commented Feb 19, 2012 at 19:10

Alternatively, use a tiny FPGA and the clock manager within it, many of which can provide all four quadrant clocks duty-cycle corrected. For example see figure 2-2 in the Xilinx clocking user guide for Spartan-6.

enter image description here

It might be a bit of a waste if you can't find a use for the actual logic inside it though

(However I just checked the datasheet and, irritatingly for you, it only operates down to 5MHz - I'll leave this answer up in case it's of interest to future viewers operating at higher frequencies!)


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