I am experimenting with moderately high frequency circuits, so decided to analyze, build and test an amplifier. This is the circuit:

Q1 is a CE amplifier, Q2 is Emitter follower to buffer the load. R2-R4 bias the transistors and R4 provides negative feedback. Due to negative feedback, the input impedance of this amplifier is quite low and a strong function of gain. Nonetheless, the 50ohm source is terminated by a 50ohm R6.RLOAD is set to 50.

The transistors in use are the BC547Bs, Ft = 300Mhz, Cbe = 18pf, Cbc = 4pf from the datasheet.

The goal is to build an amplifier that has a reasonably flat response from 1 MHz to about 40 MHz.

Here is the small signal circuit I think applies here and my calculations:

enter image description here

I calculated a gain of about 30 with the Load present and SPICE backs me up. I calculated the -3dB point and that came to about 120 MHz, due to the Miller Impedance of the feedback network, in parallel with R1. SPICE confirms this calculation also.

Here is the circuit all built up:

enter image description here

Here is how I probed everything, the probes are x10, and the scope is a 100 MHz Rigol.

enter image description here

The results are quite perplexing and I’m trying to find out why the theory is not matching with the circuit. At 1 MHz, the gain I measure is about 25, and a theoretical gain of about 30. This isn’t too bad. The trouble is the frequency response is very unexpected. The gain starts to roll off sharply after about 3 MHz, and the -3dB registers at about 16 MHz.

The roll off is at about 15% of the frequency calculated! Possible explanations I have are:

The transistors are not suitable: The transistors are standard BC547s with a transition frequency of about 300 MHz. I have taken into account the junction capacitances so I don’t see why they roll off would happen so early.

The resistors I have used are not suited for high frequency operation: I am not sure about this one, I am using carbon film resistors which should have reasonable low inductances for reliable sub 100 MHz operation (?)

Measurement setup is not correct: This might be possible, as I really don’t have experience measuring high frequency circuits properly. Both input and output measurements are taken with an x10 probe with the standard ground clip. The output is terminated at 50 ohms right at the output. I tried a direct BNC cable to measure the output instead of a probe, but that made things worse in terms of gain loss and distortion. I tried the springy ground tip for the probes, which made no difference.

EDIT: The physical circuit does not show a capacitor C1, this is because i was trying to eliminate a possible bad output capacitor. The results outlined above are WITH a capacitor C1 in place.

EDIT 2: After a lot of thought provoking input, i believe i am alot closer to understanding why i am "missing" gain. Ali Chen aptly pointed out the presence of power lead inductance, and after adding that to the sim model, it has bought a smile to my face. Consider the 2 frequency response of gain. The blue trace is with lead inductance, the green without. Most recently i measured a gain of 5 at 40Mhz and the model predicts a gain of about 8 when lead inductance is taken into account!

enter image description here

  • \$\begingroup\$ Your schematic shows a capacitor, C1, in series with the output. But I don't see it in your physical circuit. That's going to change the bias point of Q2 quite a bit. \$\endgroup\$ – The Photon Nov 8 '16 at 17:35
  • \$\begingroup\$ Also, try reducing the size of your photos before uploading so every reader doesn't have to download a humongous image file. \$\endgroup\$ – The Photon Nov 8 '16 at 17:37
  • \$\begingroup\$ Sorry about that, i was eliminating a possible bad output capacitor. The results outlined above were with a capacitor C1. Ill edit that in. \$\endgroup\$ – Adil Malik Nov 8 '16 at 17:41
  • \$\begingroup\$ +1 for providing a lot of info and GOOD photographs, nice one. \$\endgroup\$ – Wossname Nov 8 '16 at 18:09
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    \$\begingroup\$ :-) the first thing that came across my mind, while reading the (well formulated) question: hell the BC547 and friends were traditionally a bunch of low-frequency transistors, for audio and some such (general purpose). Never mind the 300 MHz f_t. So much for my gut feeling. Other than that, this is an interesting question that has attracted some interesting and well-informed responses :-) \$\endgroup\$ – frr Nov 8 '16 at 20:17

The problem with this prototype is in the absence of bypass capacitance on power rail. If a model for power lead of 30cm in length (400nH inductance) is added to LTspice simulations, the output does match observations - -3dB fall-off at 15 MHz. enter image description here

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  • \$\begingroup\$ Thankyou for taking the time to model this in spice! Because of the low input impedance of the circuit, it would be nice if you could show another trace of V(out)/V(in) to show the gain? \$\endgroup\$ – Adil Malik Nov 8 '16 at 20:29
  • \$\begingroup\$ Vin in my SPICE shows as flat 10mV line, taken at R7 point. \$\endgroup\$ – Ale..chenski Nov 8 '16 at 20:33
  • \$\begingroup\$ Ah, you seemed to have forgotten the 50 ohm output impedance of the source? \$\endgroup\$ – Adil Malik Nov 8 '16 at 20:42
  • \$\begingroup\$ Yes, my source was zero Ohms, correct. However, changing it to 50 Ohms does not change the fundamental issue. The Vin goes higher in the 20-50MHz area, but the gain (Vout/Vin) remains the same, dropping after 10MHz. Since we don't know the length of your wire leads, 400nH was a guess. If inductance is bigger, drop in gain is also bigger. \$\endgroup\$ – Ale..chenski Nov 8 '16 at 21:22
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    \$\begingroup\$ My model says 28.5 gain flat from 300kHz to 3MHz, and ~19 at 40 MHz. This is with bypass cap C5 at 0.1uF. But you did show the picture from LTspice, why don't you experiment with your model? What kind of caps did you add? \$\endgroup\$ – Ale..chenski Nov 8 '16 at 21:33

The transistors are standard BC547s with a transition frequency of about 300 MHz.

There's the main problem. At 300 MHz, the current gain is unity i.e. there is no amplification. Working backwards from fT towards DC, current gain rises at 20 dB/decade and, at (say) 30 MHz, the current gain will only be 20 dB or 10.

Here's a graph of what I mean (but for a much faster transistor): -

enter image description here

This will not produce the voltage gain you require and will be quite a bit below your expectations for a gain of 30 at 40 MHz. I can't tell you why your sim didn't show this up - maybe try looking at the BC547 model it uses.

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  • \$\begingroup\$ Ok it makes sense, but i dont understand why this conclusion could not be seen from the small signal model? If i understand correctly, the presence of fT is modeled by Cbe and Cbc? \$\endgroup\$ – Adil Malik Nov 8 '16 at 18:04
  • \$\begingroup\$ @AdilMalik using a sim unfortunately is not a replacement for thinking in many cases. Don't get me wrong, everyone falls into the sim trap now and then. Also, fT is measured with the collector tied to a voltage source so that miller capacitor effects are not allowed to disturb things. \$\endgroup\$ – Andy aka Nov 8 '16 at 18:09
  • \$\begingroup\$ I never use sim, and always prefer building circuits. The reason i checked with sim after was because my circuit wasnt performing as per the analysis. I still do not understand where exactly in my SS model the effect of fT been ignored? \$\endgroup\$ – Adil Malik Nov 8 '16 at 18:13
  • \$\begingroup\$ @AliChen who are you addressing? The gain of 30 is voltage gain so it's a little more complex than that. \$\endgroup\$ – Andy aka Nov 8 '16 at 18:28

Here is another way to look at Cbc. If the base end of this capacitor goes up 1mv the voltage at the collector goes down gm*RL. Looking from the base, this has the effect of making the capacitor look much larger. This is the Miller effect. The way this is usually taken into account is to put and equivalent capacitor in parallel with Cbe. Using your numbers the equivalent capacitance is (1+gmRl)*Cbc = (1+036*220)*4pF = 321pF. Now to do a rough calculation, there is a pole at 1/(2*piRsCin) = 1/(2*pi*25*339) = 18.8 MHz. From this crude calculation it sees to explain the 16MHz. Cbe is added to the new equivalent capacitor here.

The common solution to this problem is to use a cascode amplifier. This means following the common emitter stage with a common base stage. The cascode stage has no voltage change at the common emmitter stage collector so the capacitance is not multiplied.

If you are stuck with 5V a cascode may be difficult to bias. The usual solution to this problem is to use a folded cascode. A folded cascode implements the common base stage with a PNP. You would still follow this with a common collector stage.

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  • \$\begingroup\$ I agree and follow, with what you said. However, why have you ignored the effect on this pole by the feedback resistor (R4 + rbe2)? This will also "feel" the miller effect and would become (220+440)/Av?, thus pushing the pole further up in frequency. The gain in this case is not gmRl because of feedback. Rl is effectively, Rl // 220 + rbe2 // Z,Cbc, so the gain is considerably less than gmRl. Furthermore, the Input resistance that sets the pole is, 25//100//((220+rbe2)/Av) = 7 when the Av for the miller effect is about 60. This sets the pole at about 100 Mhz i believe? \$\endgroup\$ – Adil Malik Nov 8 '16 at 19:34
  • \$\begingroup\$ Since everybodys experience is different we need to agree on some terms to make sure we understand each other. I view this as a shunt shunt feedback amplifier so its gain is Vout/Iin. I don't get 25 for this. If you want to take this view this as a voltage amplifier then the gain would be Vout/Vin where Vin is at the opposite end of the 25 Ohm resistor from the base. If you buy that, then I think the voltage gain is trying to be -Vin*220/25. What you are calling is Av if the close to the forward gain. Would you agree that rbe2 and R2 included in Av calculation should be time beta? \$\endgroup\$ – owg60 Nov 8 '16 at 23:35
  • \$\begingroup\$ Yes, i am looking at this as a voltage amplifier. I dont quite understand why rbe2 and R2 should be times beta? Are you saying that because of the effect of the emitter follower? The way i look at it is: Due to the emitter follower, R2 (and any RLoad) appears very large (beta times larger to be exact), so i ignore it completely from the gain calculation. Then the feedback resistance is effectively R4 + rbe2. This resistance appears in parallel with R1, to form the Rl in your gmRl. This is what ive done in the SS model i drew. I believe this is correct? \$\endgroup\$ – Adil Malik Nov 9 '16 at 10:41
  • \$\begingroup\$ Yes R2||RL are multiplied by the beta of the transistor. When a emitter follower is called a buffer, it is because it tends isolate the load from the previous stage. look at it this was, if 100mV appears at the base and the emitter responds with say 999.5mV is any current really going form the base through the load? --- OK, if you are looking at this as a voltage amplifier, where are you measuring the input voltage? The feedback makes the input look very low impedance. If you are looking at the other side of the 25 Ohm then the gain should be -220/25, except this is not an ideal opamp. \$\endgroup\$ – owg60 Nov 9 '16 at 11:09
  • \$\begingroup\$ I am measuring it at the base of the transistor Q1 \$\endgroup\$ – Adil Malik Nov 9 '16 at 12:37

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