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I hope this is the place to ask such a question.

Given a shift register- within 8 clock pulses 8 bits will enter this register, I need to make a circuit with this register, and other 3 flip-flops such that its exit line would be 1 if the first 4 bits are equal to the last 4.

This is an example of possible solution.

My question for you is: How come that only at the end of the 8th pulse a value would go out to the "equal" line? (or that in this solution- successes consider as output of "1111"?)

enter image description here

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  • \$\begingroup\$ How long is the shift register? 4 bits? 8 bits? something else? With a 4 bit register and all 4 bits available externally, consider using the three FFs as a counter,initialized to 0, that counts clock pulses. The register output is fed back and XORed into the bit going in when the counter high-order bit is 1, so during the first 4 clock cycles, the register fills with x0, x1, x2, x3, while during the next 4, it fills with x4 XOR x0, x5 XOR x1, x6 XOR x2 and x7 XOR x3 = 0000 exactly when bits match. Detect with a 4-input NOR whose output is looked at only when the counter contains 111. \$\endgroup\$ – Dilip Sarwate Feb 19 '12 at 18:27
  • \$\begingroup\$ "How come that only at the end of the 8th pulse a value would go out .." -- how can you tell if the 1st four are the same as the last four until you've seen all 8? With one bit per clock, that's 8 clocks. Just not clear what the question is. \$\endgroup\$ – JustJeff Mar 21 '12 at 2:13
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What exactly are you given to work with? Your diagram shows some gates in addition to the shift register and the flip flops. If the shift register bits are all exposed, you could simply use four XOR gates and a quad OR or NOR gate. No flip flops required. Otherwise, do you need to know, at any given time, whether the last four inputs match the previous four, or will you only need to ascertain that every four clock pulses, or every eight, or what?

Conceptually, I think your best bet may be to use your flip flops to make a counter which will increment up to a max of four whenever the input to the shift register matches the signal four previous, and will reset to zero otherwise. Without understanding the exact requirements, though, it's hard to say for sure.

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