I am asked to design a 4-bit signed multiplier using only combinational circuits. Verilog code.

I have designed a 4 bit multipler:

The Half adder module

module HA(sout,cout,a,b);   //for Half adder mux
 output sout,cout;
 input a,b;
 assign sout=a^b;
 assign cout=(a&b);

The Full adder module

module FA(sout,cout,a,b,cin);   // for full adder mux
 output sout,cout;
 input a,b,cin;
 assign sout=(a^b^cin);
 assign cout=((a&b)|(a&cin)|(b&cin));

The multiply module

module multiply4bits(product,inp1,inp2);
 output [7:0]product;
 input [3:0]inp1;
 input [3:0]inp2;
 assign product[0]=(inp1[0]&inp2[0]);

 wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17; //wire range started from [1:17]

 HA HA1(product[1],x1,(inp1[1]&inp2[0]),(inp1[0]&inp2[1]));
 FA FA1(x2,x3,inp1[1]&inp2[1],(inp1[0]&inp2[2]),x1);
 FA FA2(x4,x5,(inp1[1]&inp2[2]),(inp1[0]&inp2[3]),x3);
 HA HA2(x6,x7,(inp1[1]&inp2[3]),x5);
 HA HA3(product[2],x15,x2,(inp1[2]&inp2[0]));
 FA FA5(x14,x16,x4,(inp1[2]&inp2[1]),x15);
 FA FA4(x13,x17,x6,(inp1[2]&inp2[2]),x16);
 FA FA3(x9,x8,x7,(inp1[2]&inp2[3]),x17);
 HA HA4(product[3],x12,x14,(inp1[3]&inp2[0]));
 FA FA8(product[4],x11,x13,(inp1[3]&inp2[1]),x12);
 FA FA7(product[5],x10,x9,(inp1[3]&inp2[2]),x11);
 FA FA6(product[6],product[7],x8,(inp1[3]&inp2[3]),x10);

I think that is right, but now I need to extend it and add 2's complement at the end?

  • \$\begingroup\$ Have you tried running simulation? \$\endgroup\$ – Greg Nov 9 '16 at 15:01
  • \$\begingroup\$ I did simulation but it shows me error! \$\endgroup\$ – fa6ma Nov 9 '16 at 18:39
  • \$\begingroup\$ Look for Pezaris or Baugh-Wooley multipliers, for example eee.guc.edu.eg/Courses/Electronics/… \$\endgroup\$ – TEMLIB Nov 12 '16 at 11:12

A simple approach would be to convert both factors to sign/magnitude representation. Be sure to use 1 bit for sign and 4 for magnitude to avoid overflow for the value -8. XOR the signs and apply that to the result. This can be done in another verilog module, wrapping your multiply4bits-module.

This combinatorial function will probably be optimized to something completely different when you look at the synthesis result. There are far better approaches when you want to optimize for resources or delay. Look at this excellent paper by Ray Andraka for an overview.

In your case, Booth's algorithm would be a good approach.


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