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I want to output a signal through the SMA connector available on the Spartan 3E starter kit board. Can someone guide me as to how to do it?

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    \$\begingroup\$ A link to the board data sheet or user's guide would help. Also, what have you already tried, and in what way didn't it work? \$\endgroup\$ – The Photon Feb 19 '12 at 16:09
  • \$\begingroup\$ I have gone through the documentation available with the kit and it doesnt seem to have that information. I have already written the VHDL code which generates the signal. I just need to set the output to the SMA connector. I think there would be a certain register which needs to be used to enable the output through the SMA. Unfortunately, I do not know how to do it nor can I find it. \$\endgroup\$ – Neel Mehta Feb 19 '12 at 16:36
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    \$\begingroup\$ Do you have a schematic of the board? \$\endgroup\$ – The Photon Feb 19 '12 at 16:48
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    \$\begingroup\$ Question should be closed if no details of the board are provided! \$\endgroup\$ – Leon Heller Feb 19 '12 at 18:10
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    \$\begingroup\$ xilinx.com/products/boards-and-kits/HW-SPAR3E-SK-US-G.htm \$\endgroup\$ – Neel Mehta Feb 20 '12 at 4:44
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There is only one Spartan 3E Starter Kit Board. The PDF is below. http://www.xilinx.com/support/documentation/boards_and_kits/ug230.pdf

From the PDF:

"The SMA connector allows an external clock source to drive one of the FPGA’s global clock inputs. Alternatively, the FPGA can provide a high-performance clock to another board via the SMA connector. See Chapter 3, “Clock Sources,” for additional information."


NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ;
NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ;

Figure 3-2: UCF Location Constraints for Clock Sources


The UCF file is how you set a signal to a pin. Is this the info you're missing?

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  • \$\begingroup\$ The section on "Clock sources" is for generating the clock and setting it to output via SMA connector or taking an external clock and providing it as an input to the FPGA via SMA. It does not mention how to set a generated signal to the output via SMA connector. \$\endgroup\$ – Neel Mehta Feb 20 '12 at 4:47
  • \$\begingroup\$ P. 21 - SMA is located on FPGA Pin A10. If your signal name is foo then your UCF should be NET "foo" = "A10" | IOSTANDARD = LVCMOS33; \$\endgroup\$ – spearson Feb 20 '12 at 6:54

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