It's theoretical and stupid question.

In my example Master and Slaves have 8-bit shift registers. I can't understand how to receive data from second slave.
enter image description here

Is the below algorithm right?

  1. Master lowers /SS signal.
  2. Master writes 16 zero bits to MOSI (Slave 1 and Slave 2 will contain 8 zero bits, data from Slave 2 will shift to Master).
  3. Master have to high /SS signal.
  4. Read received data from Master.

I was embarrassed that SPI is full duplex interface. I thought that Master must to send only valid data to slaves (not zero or trash).

  • 1
    \$\begingroup\$ I think you took picture from here en.wikipedia.org/wiki/…, it has explanation and also note that in order for this config to work, all devices in chain should support the protocol. \$\endgroup\$
    – Anonymous
    Commented Nov 10, 2016 at 14:17
  • \$\begingroup\$ @Anonymous You're right, I took picture from wiki. I understand how to send. But how receive data only from 2nd slave? How many tacts master must wait? \$\endgroup\$ Commented Nov 10, 2016 at 14:34
  • \$\begingroup\$ The slave select will determine this. You can either have a pin that will be attached to all the slaves at the same time which may be more tedious since you don't quite know where the receive data is coming from. Also, you can have a IO pin on your Master for each Slave Select. You would only have to change the state of pin 1 to control slave 1, pin 2 to control slave 2, and so on. SPI will have parts preconfigured to work with each other most of the time. Read the following tutorial and that should help you out. learn.sparkfun.com/tutorials/serial-peripheral-interface-spi \$\endgroup\$
    – 12Lappie
    Commented Nov 10, 2016 at 14:49

1 Answer 1


Yes it looks fine. You have to consider all SPI nodes, including the master, to be 8 bit shift registers, that are connected in a circle. Indeed all communication is full duplex.

The master will have a tx and a rx data register, but it also has a shift register which is separate from these. If you check the SPI chapter of any MCU manual, there is usually some helpful schematics that explain how this works internally.

Whenever you produce 8 clock edges by sending 1 byte of data from the master, whatever data that happened to be in the 1st slave will get transferred to the 2nd slave and so on.

Lets say that the slaves have the data 0xAA, 0xBB and 0xCC respectively. The master sends out data 0xFF. After the transmission, the master rx data register will contain 0xCC, and the slaves will have data 0xFF, 0xAA and 0xBB.

This means that you have to send 3 bytes of data in order to read from all 3 slaves.

Some things to be extra careful with:

  • Check how the master clears tx/rx flags. Sometimes these are cleared by writes or reads, which could cause unexpected behavior (and also cause in-circuit debuggers to hang up your SPI when they are reading the SPI register map).

  • Check expected clock polarity of all devices involved. Check "clock phase" settings (clock data on edge or at center of a data byte). Wrong settings here and you get "clock skew", which causes subtle misbehavior.

  • SPI is unfortunately very poorly standardized. So look out for non-standard crap. Many of the major semiconductor companies love "crap SPI". Some devices require you to insert delays here and there in order for them to work. Others require weird pulses on the SS line. Etc etc. The market is full of such crap.

  • 1
    \$\begingroup\$ Perhaps the most important thing to add, which you've hinted at in your answer, is although 16 clocks is enough to read the 2nd slave, it will leave the 3rd slave's register containing whatever the first slave shifted out. If it interprets this as a valid control code, then it will do something unintended. Better to always provide all 24 clocks, and leave all slaves in a master-defined state. You might be lulled into a false sense of security with one type of slave 1, then change to another type and suddenly your slave 3 misbehaves for 'no reason'. \$\endgroup\$
    – Neil_UK
    Commented Nov 11, 2016 at 7:05

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