Yes it looks fine. You have to consider all SPI nodes, including the master, to be 8 bit shift registers, that are connected in a circle. Indeed all communication is full duplex.
The master will have a tx and a rx data register, but it also has a shift register which is separate from these. If you check the SPI chapter of any MCU manual, there is usually some helpful schematics that explain how this works internally.
Whenever you produce 8 clock edges by sending 1 byte of data from the master, whatever data that happened to be in the 1st slave will get transferred to the 2nd slave and so on.
Lets say that the slaves have the data 0xAA, 0xBB and 0xCC respectively. The master sends out data 0xFF. After the transmission, the master rx data register will contain 0xCC, and the slaves will have data 0xFF, 0xAA and 0xBB.
This means that you have to send 3 bytes of data in order to read from all 3 slaves.
Some things to be extra careful with:
Check how the master clears tx/rx flags. Sometimes these are cleared by writes or reads, which could cause unexpected behavior (and also cause in-circuit debuggers to hang up your SPI when they are reading the SPI register map).
Check expected clock polarity of all devices involved. Check "clock phase" settings (clock data on edge or at center of a data byte). Wrong settings here and you get "clock skew", which causes subtle misbehavior.
SPI is unfortunately very poorly standardized. So look out for non-standard crap. Many of the major semiconductor companies love "crap SPI". Some devices require you to insert delays here and there in order for them to work. Others require weird pulses on the SS line. Etc etc. The market is full of such crap.